A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Table 3

Resource savings (LUTS) of FD-FTA heuristic compared to previous work for 100% and 70% EC.

Benchmark	Normalized latency and EC% constraints
	1.0x		1.2x		1.4x		1.6x		1.8x		2.0x
	100%	70%	100%	70%	100%	70%	100%	70%	100%	70%	100%	70%
lapjacobi	0%	0%	0%	0%	2%	28%	−2%	−2%	−5%	−6%	−2%	−42%
lapsor	19%	19%	−1%	−1%	1%	−5%	1%	−2%	0%	−38%	0%	−33%
conv5x5	0%	0%	40%	41%	49%	56%	54%	59%	53%	64%	59%	63%
fft8	−5%	−5%	10%	9%	12%	27%	17%	22%	22%	29%	36%	35%
fftRadix4	0%	−2%	−6%	11%	12%	22%	9%	30%	12%	31%	13%	27%
fft16	−3%	−1%	15%	28%	9%	18%	11%	25%	−9%	6%	18%	27%
linjacobi	−1%	0%	29%	32%	24%	41%	43%	52%	44%	53%	42%	54%
linsor	0%	7%	−7%	−12%	−8%	−1%	−18%	−33%	−20%	−33%	−46%	−25%
conv9x9	−1%	0%	38%	38%	57%	63%	61%	67%	69%	72%	67%	74%
Average	1%	2%	13%	16%	18%	28%	20%	24%	18%	20%	21%	20%
small0	1%	1%	1%	1%	0%	4%	0%	4%	−21%	−10%	26%	40%
small1	0%	1%	0%	1%	0%	1%	2%	2%	2%	2%	0%	−35%
small2	0%	0%	0%	0%	11%	13%	11%	13%	−1%	12%	13%	15%
small3	0%	0%	0%	0%	34%	30%	25%	24%	1%	19%	20%	−4%
small4	10%	35%	10%	35%	11%	11%	15%	−5%	−18%	−25%	−4%	−4%
small5	27%	45%	28%	48%	22%	31%	−2%	−1%	3%	0%	−1%	−25%
small6	2%	2%	2%	2%	−1%	10%	11%	22%	1%	−1%	−11%	−19%
small7	0%	0%	0%	0%	28%	32%	34%	42%	43%	52%	46%	51%
medium0	0%	0%	33%	39%	44%	46%	44%	48%	49%	53%	40%	50%
medium1	0%	−2%	27%	40%	42%	48%	43%	47%	49%	53%	48%	53%
medium2	0%	0%	37%	41%	50%	53%	55%	60%	56%	60%	58%	63%
medium3	0%	0%	27%	33%	38%	43%	41%	48%	42%	49%	39%	49%
medium4	0%	0%	31%	35%	39%	48%	43%	47%	46%	52%	48%	52%
Average	3%	6%	15%	21%	24%	28%	25%	27%	19%	24%	25%	22%
Total average	2%	4%	14%	19%	22%	28%	23%	26%	19%	23%	23%	21%