Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

<div class="floats-full-page floats-full-page-figure"><h2>Figure 11</h2><div class="floats-full-page-caption"><div>Average area savings for <svg height="8.8423pt" id="M124" style="vertical-align:-0.2064009pt" version="1.1" viewbox="-0.0498162 -8.6359 38.4976 8.8423" width="38.4976pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M822 650H589L583 622C660 617 677 607 674 561C672 534 664 481 647 390L600 137H596L273 650H126L120 622C176 620 194 615 207 594C221 571 225 557 214 504L161 257C141 166 129 112 121 85C108 42 83 30 29 28L23 0H260L266 28C193 33 173 42 176 89C178 122 186 172 202 255L256 527H259L583 -8H612L690 390C708 481 720 535 728 558C744 603 756 619 816 622L822 650Z" id="g113-79"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="839" vert-adv-y="839" xpluscharwidth="10.907"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,14.542,0)"><path d="M535 323V373H52V323H535ZM535 138V188H52V138H535Z" id="g117-34"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="587" vert-adv-y="587" xpluscharwidth="22.173000000000002"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,25.805,0)"><path d="M384 0V27C293 34 287 42 287 114V635C232 613 172 594 109 583V559L157 557C201 555 205 550 205 499V114C205 42 199 34 109 27V0H384Z" id="g113-50"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="480" vert-adv-y="480" xpluscharwidth="32.045"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,32.045,0)"><path d="M241 635C89 635 35 457 35 312C35 153 89 -12 240 -12C390 -12 443 166 443 312C443 466 390 635 241 635ZM238 602C329 602 354 454 354 312C354 172 330 22 240 22C152 22 124 173 124 313S148 602 238 602Z" id="g113-49"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="480" vert-adv-y="480" xpluscharwidth="38.285000000000004"></glyph.data></g></svg> and <svg height="9.49473pt" id="M125" style="vertical-align:-0.2063999pt" version="1.1" viewbox="-0.0498162 -9.28833 6.66314 9.49473" width="6.66314pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M480 416C480 431 465 448 438 448C388 448 312 383 252 330C217 299 188 273 155 237H153L257 680C262 700 263 712 253 712C240 712 183 684 97 674L92 648L126 647C166 646 172 645 163 606L23 -6L29 -12C51 -5 77 2 107 8C115 62 130 128 142 180C153 193 179 220 204 241C231 170 259 106 288 54C317 0 336 -12 358 -12C381 -12 423 2 477 80L460 100C434 74 408 54 398 54C385 54 374 65 351 107C326 154 282 241 263 299C296 332 351 377 403 377C424 377 436 372 445 368C449 366 456 368 462 375C472 386 480 402 480 416Z" id="g113-108"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="503" vert-adv-y="503" xpluscharwidth="6.539"></glyph.data></g></svg> = 4–7 over the 20 MCNC benchmark circuits.</div></div><div class="floats-full-page-content"><table class="figure-group"><tr class="fig-image"><td><object data="https://static-01.hindawi.com/articles/ijrc/volume-2017/7021056/figures/7021056.fig.0011.svgz" name="7021056.fig.0011" type="image/svg+xml"></object></td></tr></table></div></div>

Figure 11 | Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

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Figure 11: Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

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Figure 11

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