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International Journal of Reconfigurable Computing
Volume 2017, Article ID 7802735, 8 pages
Research Article

Challenges in Clock Synchronization for On-Site Coding Digital Beamformer

Department of Electrical and Computer Engineering, Florida International University, Miami, FL 33174, USA

Correspondence should be addressed to Satheesh Bojja Venkatakrishnan; ude.uso@1.nanhsirkataknevajjob

Received 30 May 2017; Revised 27 August 2017; Accepted 17 September 2017; Published 25 October 2017

Academic Editor: John Kalomiros

Copyright © 2017 Satheesh Bojja Venkatakrishnan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.