International Journal of Reconfigurable Computing / 2018 / Article / Fig 2

Research Article

Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

Figure 2

(a) An overview of the DRAM hierarchy. (b) Image showing the structure of a single DRAM bank. (c) Flow chart explaining additional latency introduced when a new row has to be referred to in the row buffer to access a specific element.
(a) DRAM hierarchy
(b) Single DRAM bank
(c) Row buffer hit and miss

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