International Journal of Reconfigurable Computing / 2018 / Article / Tab 3

Research Article

Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

Table 3

DRAM energy consumption baseline vs tile-hopping.


EPR CW Read
(Baseline) 4.46 5.77 7.12

EPR CW Read
Tile-Hopping 2.54 2.95 3.36
(Proposed)

Reduction

Energy per read (EPR).
Column-wise memory access (CW).

We are committed to sharing findings related to COVID-19 as quickly as possible. We will be providing unlimited waivers of publication charges for accepted research articles as well as case reports and case series related to COVID-19. Review articles are excluded from this waiver policy. Sign up here as a reviewer to help fast-track new submissions.