International Journal of Reconfigurable Computing / 2018 / Article / Tab 5

Research Article

Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL

Table 5

The optimization results.

Optimization MethodsFFsLUTsDSPsBlock RAMsTime(ms)


Loop Pipeline53748814161850.0

Loop Unroll553310214161827.9

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