Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL

Table 8

The resources of every compute unit on FPGA.

Layer	FFs	LUTs	DSPs	Block RAMs
C12	8331	11762	19	20
S2	6967	10672	15	31
C33	8160	15935	17	18
S4	6777	10071	15	9
C5	7141	11593	16	136
F6	6637	10341	15	10
O7	5087	4488	12	4
SUM()	74751(8.63%)	118494(27.32%)	145(4.03%)	284(19.32%)