Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

Table 1

Resource utilization.

	Slice LUTs	Slice registers	Slice	Lut Flip Flop	Block RAM	DSPs
The total system	10823	14524	4689	5121	10.5	19
AXI performance Monitor	2787	3504	1135	1079	0	0
Clock reset	19	40	14	15	0	0
Processing system	538	655	226	284	0	0
Video-out	239	355	126	103	1	0
RGB to YCrCb	365	335	144	163	0	4
Video Timing Controller	131	212	78	39	0	0
Video pipe (VDMA)	5886	8371	2514	3042	9.5	12