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International Journal of Reconfigurable Computing
Volume 2018, Article ID 3214679, 16 pages
Research Article

Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator

1Department of Industrial Sciences (INDI), Vrije Universiteit Brussel (VUB), Brussels, Belgium
2Escuela Superior Politecnica del Litoral (ESPOL), Guayaquil, Ecuador

Correspondence should be addressed to Bruno da Silva;

Received 15 October 2017; Revised 9 February 2018; Accepted 4 March 2018; Published 2 May 2018

Academic Editor: João Cardoso

Copyright © 2018 Bruno da Silva et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The current Microelectromechanical Systems (MEMS) technology enables the deployment of relatively low-cost wireless sensor networks composed of MEMS microphone arrays for accurate sound source localization. However, the evaluation and the selection of the most accurate and power-efficient network’s topology are not trivial when considering dynamic MEMS microphone arrays. Although software simulators are usually considered, they consist of high-computational intensive tasks, which require hours to days to be completed. In this paper, we present an FPGA-based platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network’s topology, or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. The platform is designed to exploit the FPGA’s partial reconfiguration feature to increase the flexibility of the network emulator as well as to increase performance thanks to the use of the PCI-express high-bandwidth interface. On the one hand, the network emulator presents a higher flexibility by partially reconfiguring the nodes’ architecture in runtime. On the other hand, a set of strategies and heuristics to properly use partial reconfiguration allows the acceleration of the emulation by exploiting the execution parallelism. Several experiments are presented to demonstrate some of the capabilities of our platform and the benefits of using partial reconfiguration.