International Journal of Reconfigurable Computing / 2018 / Article / Lst 1

Research Article

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Listing 1

Input/output types for RMs.
1 type RecRegSigIOType8 = Signal ( BitVector 8 )
2 type RecRegSigIOType16 = Signal ( BitVector 16 )
3 type RecRegSigIOType32 = Signal ( BitVector 32 )
4 type RecRegSigIOType64 = Signal ( BitVector 64 )
5 type RecRegSigIOType65 = Signal ( BitVector 65 )