Research Article
Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions
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Input/output types for RMs.
| 1 type RecRegSigIOType8 = Signal ( BitVector 8 ) | | 2 type RecRegSigIOType16 = Signal ( BitVector 16 ) | | 3 type RecRegSigIOType32 = Signal ( BitVector 32 ) | | 4 type RecRegSigIOType64 = Signal ( BitVector 64 ) | | 5 type RecRegSigIOType65 = Signal ( BitVector 65 ) |
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