International Journal of Reconfigurable Computing / 2018 / Article / Tab 2

Research Article

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Table 2

Synthesis results on Zynq-7000 FPGA.

Name FFs LUTs Max Frequency (MHz)

4 15 833
35 108 455
19 24 733
43 80 570
1 3 1221
35 125 450
3 4 940
5 11 841
1 3 1221
3 4 1131
1 2 1221
72 168 450
60 217 470
50 111 460
62 125 501
80 240 431
62 129 501
81 225 423
61 170 423