Research Article
RP-Ring: A Heterogeneous Multi-FPGA Accelerator
Table 1
The parameters of the boards.
| | Board | Main chip | Hard CPU | Logic cells | Flip flop | Block RAM | DSP slice | Memory access bandwidth (theoretical) | Connection |
| | Zedboard | XC7Z020 | Cortex A9 Dual Core | 85,000 | 106,400 | 560 Kb | 220 | 8.5 GB/s | Ethernet | | KC705 | XC7K325T | No | 326,080 | 407,600 | 4000 Kb | 840 | 12.8 GB/s | Ethernet and SMA | | XUPV5 | XC5VLX110T | No | 46,080 | 28,800 | 1728 Kb | 48 | 3.2 GB/s | Ethernet and SMA | | Gemini-1 | XC6VLX365T ×2 | No | 364,032 each | 455,040 each | 14,976 Kb each | 576 each | 12.8 GB/s each | SMA | | Jetson-TK1 (host computer) | Tegra K1 | Cortex A15 Quard Core | — | — | — | — | — | Ethernet |
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