International Journal of Reconfigurable Computing / 2019 / Article / Tab 1

Research Article

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 1

Gate information for problems.

ProblemLayersInput wiresOutput wiresANDsXORsGates# Reprogram

6 bit adder17126624301
10 bit HD22201020901101
30 bit HD276030602703306
50 bit HD321005010045055010
8 bit mult57161612035247212
16 bit mult12132324961472196850
32 bit mult2496464201660168032201
64 bit mult50512812881282432032448813
10 4 bit sorting27840408484638548685
4 bit m_mult2510020039001160015500390
4 bit m_mult2740080075262248930015753
8 bit m_mult572004001580047200630001580
8 bit m_mult57800160012720038080050800012720
4 bit m_mult3716003200254400761600101600025440

Article of the Year Award: Outstanding research contributions of 2020, as selected by our Chief Editors. Read the winning articles.