Research Article
SIFO: Secure Computational Infrastructure Using FPGA Overlays
Table 10
Using 2 address registers for 3 addresses.
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10 AND and 10 XOR overlay cells; 300 MHz main clock and 200 MHz local clock; PR represents Page Rank. |
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10 AND and 10 XOR overlay cells; 300 MHz main clock and 200 MHz local clock; PR represents Page Rank. |