Research Article

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 10

Using 2 address registers for 3 addresses.

Problem1 reg as 1 address2 regs as 3 addressesImprovementTotal speedup

2 PR41044373581.112.47
3 PR66409585871.1310.27
4 PR900877.831.067.83

10 AND and 10 XOR overlay cells; 300 MHz main clock and 200 MHz local clock; PR represents Page Rank.