SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 7

Directly used policy using block RAM and DDR Hybrid Memory.

Problem	10 AND + hybrid memory (µs)	Speedup
6 bit adder	54	57.2
10 bit HD	88	28.8
30 bit HD	193	21.1
50 bit HD	302	21.4
8 bit mult	380	24.3
16 bit mult	1284	11.3
32 bit mult	4208	8
64 bit mult	15945	9.6
10 4 bit sorting	2292	9.2

Hybrid memory consisting of block RAM on FPGA and DDR on board.