International Journal of Reconfigurable Computing / 2019 / Article / Tab 7

Research Article

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 7

Directly used policy using block RAM and DDR Hybrid Memory.

Problem10 AND + hybrid memory (µs)Speedup

6 bit adder5457.2
10 bit HD8828.8
30 bit HD19321.1
50 bit HD30221.4
8 bit mult38024.3
16 bit mult128411.3
32 bit mult42088
64 bit mult159459.6
10 4 bit sorting22929.2

Hybrid memory consisting of block RAM on FPGA and DDR on board.

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