International Journal of Reconfigurable Computing / 2019 / Article / Tab 1

Research Article

Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

Table 1

1D-QHT implementation results on Arria 10AX115N4F45E3SG FPGA.

Number of pixelsNumber of qubitsResource utilization (%)SDRAM (bytes)Emulation time (sec)
ALMsBRAMsDSPs

16 × 16811814 K0.00018
32 × 3210118116 K0.00071
64 × 6412118164 K0.00285
128 × 128141181256 K0.01139
256 × 2561611811 M0.04557
512 × 5121811814 M0.18226
1024 × 102420118116 M0.72905

Total chip resources: NALM = 427,200; NBRAM = 2,713; NDSP = 1,518. Total on-board SDRAM memory: 2 parallel banks of 32 GB each.

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