Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

Table 2

2D-QHT implementation results on Arria 10AX115N4F45E3SG FPGA.

Number of pixels	Number of qubits	Resource utilization (%)			SDRAM (bytes)	Emulation time (sec)
		ALMs	BRAMs	DSPs
16 × 16	8	14	9	2	4 K	0.00012
32 × 32	10	14	9	2	16 K	0.00047
64 × 64	12	14	9	2	64 K	0.00187
128 × 128	14	14	9	2	256 K	0.00746
256 × 256	16	14	9	2	1 M	0.02982
512 × 512	18	14	9	2	4 M	0.11926
1024 × 1024	20	14	9	2	16 M	0.47704

Total chip resources: N_ALM = 427,200; N_BRAM = 2,713; N_DSP = 1,518. Total on-board SDRAM memory: 2 parallel banks of 32 GB each.