International Journal of Reconfigurable Computing / 2019 / Article / Tab 2

Research Article

Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

Table 2

2D-QHT implementation results on Arria 10AX115N4F45E3SG FPGA.

Number of pixelsNumber of qubitsResource utilization (%)SDRAM (bytes)Emulation time (sec)
ALMsBRAMsDSPs

16 × 16814924 K0.00012
32 × 3210149216 K0.00047
64 × 6412149264 K0.00187
128 × 128141492256 K0.00746
256 × 2561614921 M0.02982
512 × 5121814924 M0.11926
1024 × 102420149216 M0.47704

Total chip resources: NALM = 427,200; NBRAM = 2,713; NDSP = 1,518. Total on-board SDRAM memory: 2 parallel banks of 32 GB each.

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