An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

Table 1

Convolutional parameters for the network.

	Layer	Input matrix	Filter	Cin	Cout	Output matrix
Hidden layer 0	Time_0	63 × 13	5 × 1	1	1	59 × 13
	Freq_0	59 × 13	1 × 3	1	8	59 × 11
Hidden layer 1	Time_1	59 × 11	5 × 1	8	8	55 × 11
	Freq_1	55 × 11	1 × 3	8	16	55 × 9
Hidden layer 2	Time_2	55 × 9	11 × 1	16	16	45 × 9
	Freq_2	45 × 9	1 × 3	16	192	45 × 7
	Final_conv	45 × 7	1 × 1	192	12	45 × 7