Research Article
An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick
Table 5
Hardware accelerator implementation on Xilinx FPGAs.
| FPGA family | Comb. elem. | Comb. elem. (%) | Seq. elem. | Seq. elem. (%) | BRAM | BRAM (%) | LRAM | LRAM (%) |
| Zynq US+ | 81345 | 30 | 860 | <1 | 228 | 25 | 2560 | 2 | Virtex US+ | 81367 | 21 | 864 | <1 | 228 | 32 | 2560 | 1 | Virtex US | 81427 | 23 | 952 | <1 | 228 | 18 | 2560 | 3 | Zynq-7000 | 76283 | 35 | 632 | <1 | 244 | 45 | 0 | 0 | Virtex-7 | 76163 | 37 | 632 | <1 | 244 | 33 | 0 | 0 | Kintex-7 lv | 81737 | 81 | 633 | <1 | 244 | 75 | 0 | 0 | Artix-7 lv | 87406 | 86 | 1081 | <1 | 228 | 70 | 0 | 0 |
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