Automatic Pipelining and Vectorization of Scientific Code for FPGAs

Figure 2

The TyTra backend scheduler. It reads in the TIR description of the problem, which has a syntax similar to LLVM-IR’s, using the SSA (single static assignment) format. The output of the scheduler is the dataflow graph of the problem, with buffers inferred if needed (e.g., see Figures 6 and 9), which is then used to estimate performance, as well as generate synthesizable Verilog HDL.