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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2020
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Article
/
Tab 2
/
Research Article
FPGA Implementation of A
Algorithm for Real-Time Path Planning
Table 2
Design option of three best choices.
Design option
Block size
M
Block number
N
Penalty/cycles
Cache size/KB
1
8
15
196026
38.4
2
16
12
37506
122.88
3
32
5
72380
204.8