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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2020
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Article
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Tab 3
/
Research Article
FPGA Implementation of A
Algorithm for Real-Time Path Planning
Table 3
Summarization of synthesis results.
Cells
Used
Available
Utilization (%)
Slice registers
50930
508400
10
Slice LUTs
134578
254200
52
Block RAMs
14
795
1.8
Maximum frequency
255.188 MHz