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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
/
2020
/
Article
/
Tab 5
/
Research Article
FPGA Implementation of A
Algorithm for Real-Time Path Planning
Table 5
Experimental results of randomly generated maps.
Data set
Cases
Implementation
Distance
Expanded nodes
Time (ms)
Speedup
Random 0%
Worst
Software
357
65527
85
75
Hardware
1.1367
Random
Software
136.5
29720
38.2
74
Hardware
0.516
Random 10%
Worst
Software
361.8
45284
76.4
72
Hardware
1.059
Random
Software
140.9
26278
31.2
69
Hardware
0.467
Random 20%
Worst
Software
370.2
41202
66.4
61
Hardware
1.087
Random
Software
131.8
7986
21.7
44
Hardware
0.493
Random 30%
Worst
Software
374.4
35597
58.4
50
Hardware
1.160
Random
Software
152.0
7543
20
47
Hardware
0.429
Random 40%
Worst
Software
392.2
24236
52
45
Hardware
1.144
Random
Software
155.0
6962
19.8
48
Hardware
0.412
Random 50%
Worst
Software
433.9
23352
40.4
37
Hardware
1.088
Random
Software
168.1
5882
14.2
42
Hardware
0.340