A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

Table 4

ASP circuit variants of two systems tasks.

Variant no.	No. of slots	(	Performance	Logic slices	BRAM slices	DSP slices
	1	240	120 fps	3093	43	30
	2	120	120 fps	5897	79	54
	4	60	120 fps	11779	145	97
	8	30	120 fps	23259	254	176
	1	240	16 Mbps	2061	22	82
	2	120	16 Mbps	3893	40	157
	4	60	16 Mbps	7514	58	245
	8	30	16 Mbps	14499	94	447