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Citations to this Journal [330 citations: 1–100 of 299 articles]

Articles published in International Journal of Reconfigurable Computing have been cited 330 times. The following is a list of the 299 articles that have cited the articles published in International Journal of Reconfigurable Computing.

  • Hasna Bouraoui, Chadlia Jerad, Anupam Chattopadhyay, and Nejib Ben Hadj-Alouane, “Hardware Architectures for Embedded Speaker Recognition Applications,” ACM Transactions on Embedded Computing Systems, vol. 16, no. 3, pp. 1–28, 2017. View at Publisher · View at Google Scholar
  • Aleksandra Świetlicka, Karol Gugała, Witold Pedrycz, and Andrzej Rybarczyk, “Development of the deterministic and stochastic Markovian model of a dendritic neuron,” Biocybernetics and Biomedical Engineering, 2017. View at Publisher · View at Google Scholar
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  • Miriam Guadalupe Cruz Jiménez, Uwe Meyer Baese, and Gordana Jovanovic Dolecek, “Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators,” EURASIP Journal on Advances in Signal Processing, vol. 2017, no. 1, 2017. View at Publisher · View at Google Scholar
  • Reza Ramezani, Yasser Sedaghat, Mahmoud Naghibzadeh, and Juan Antonio Clemente, “Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms,” IEEE Transactions on Aerospace and Electronic Systems, pp. 1–1, 2017. View at Publisher · View at Google Scholar
  • Felipe Tuyama De Faria Barbosa, Duarte Lopes De Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, and Jocemar Francisco De Souza Luciano, “Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 5, pp. 1064–1074, 2017. View at Publisher · View at Google Scholar
  • Cesar Carranza, Daniel Llamocca, and Marios Pattichis, “Fast 2D Convolutions and Cross-Correlations Using Scalable Architectures,” IEEE Transactions on Image Processing, vol. 26, no. 5, pp. 2230–2245, 2017. View at Publisher · View at Google Scholar
  • Nuno M. C. Paulino, Joao Canas Ferreira, and Joao M. P. Cardoso, “Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 21–34, 2017. View at Publisher · View at Google Scholar
  • Artjom Grudnitsky, Lars Bauer, and Jorg Henkel, “Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, pp. 594–607, 2017. View at Publisher · View at Google Scholar
  • Ulkuhan Guler, Ali Emre Pusane, and Günhan Dundar, “Design of efficient CMOS ring oscillator-based random number generator,” International Journal of Electronics, pp. 1–18, 2017. View at Publisher · View at Google Scholar
  • Bibin Johnson, Jiljo K. Moncy, and J. Sheeba Rani, “Self adaptable high throughput reconfigurable bilateral filter architectures for real-time image de-noising,” Journal of Real-Time Image Processing, 2017. View at Publisher · View at Google Scholar
  • Renato Coral Sampaio, José Maurício S. T. Motta, and Carlos Humberto Llanos, “An FPGA-based controller design for a five degrees of freedom robot for repairing hydraulic turbine blades,” Journal of the Brazilian Society of Mechanical Sciences and Engineering, 2017. View at Publisher · View at Google Scholar
  • Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, and Muhammad N. Marsono, “Ping-lock round robin arbiter,” Microelectronics Journal, vol. 63, pp. 81–93, 2017. View at Publisher · View at Google Scholar
  • Johanna Sepulveda, Daniel Flórez, Vincent Immler, Guy Gogniat, and Georg Sigl, “Efficient Security Zones Implementation through Hierarchical Group Key Management at NoC-Based MPSoCs,” Microprocessors and Microsystems, 2017. View at Publisher · View at Google Scholar
  • Akram Reza, “Online multi-application Mapping in photonic Network-on-Chip with mesh topology,” Optical Switching and Networking, 2017. View at Publisher · View at Google Scholar
  • Mostafa Chakir, Hicham Akhamal, and Hassan Qjidaa, “A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor,” The Scientific World Journal, vol. 2017, pp. 1–15, 2017. View at Publisher · View at Google Scholar
  • Yingjie Lao, Qianying Tang, Chris H. Kim, and Keshab K. Parhi, “Beat Frequency Detector--Based High-Speed True Random Number Generators,” ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 1, pp. 1–25, 2016. View at Publisher · View at Google Scholar
  • Zain Ul-Abdin, and Bertil Svensson, “A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing,” ACM Transactions on Reconfigurable Technology and Systems, vol. 9, no. 4, pp. 1–22, 2016. View at Publisher · View at Google Scholar
  • Bernd Bischl, Pascal Kerschke, Lars Kotthoff, Marius Lindauer, Yuri Malitsky, Alexandre Fréchette, Holger Hoos, Frank Hutter, Kevin Leyton-Brown, Kevin Tierney, and Joaquin Vanschoren, “ASlib: A benchmark library for algorithm selection,” Artificial Intelligence, vol. 237, pp. 41–58, 2016. View at Publisher · View at Google Scholar
  • M. Antonelli, L. De Micco, and H.A. Larrondo, “Measuring the Jitter of Ring Oscillators by means of Information Theory Quantifiers,” Communications in Nonlinear Science and Numerical Simulation, 2016. View at Publisher · View at Google Scholar
  • Mehdi Ayat, Hossein Hardani, Sattar Mirzakuchaki, and Farzan Haddadi, “Design and implementation of high throughput FPGA-based DVB-T system,” Computers & Electrical Engineering, vol. 51, pp. 43–57, 2016. View at Publisher · View at Google Scholar
  • Gavin Vaz, Heinrich Riebler, Tobias Kenter, and Christian Plessl, “Potential and methods for embedding dynamic offloading decisions into application code,” Computers & Electrical Engineering, 2016. View at Publisher · View at Google Scholar
  • Y.H. Moon, I.K. Eom, and S.H. Cheon, “Fast descriptor extraction method for a SURF-based interest point,” Electronics Letters, 2016. View at Publisher · View at Google Scholar
  • Michał Kierzynka, Lars Kosmann, Micha vor dem Berge, Stefan Krupop, Jens Hagemeyer, René Griessl, Meysam Peykanu, and Ariel Oleksiak, “Energy efficiency of sequence alignment tools—Software and hardware perspectives,” Future Generation Computer Systems, 2016. View at Publisher · View at Google Scholar
  • Vafa Andalibi, Francois Christophe, Teemu Laukkarinen, and Tommi Mikkonen, “Effective Connectivity Analysis in Brain Networks: A GPU-Accelerated Implementation of the Cox Method,” IEEE Journal of Selected Topics in Signal Processing, vol. 10, no. 7, pp. 1226–1237, 2016. View at Publisher · View at Google Scholar
  • Mehdi Ayat, Sattar Mirzakuchaki, and AliAsghar Beheshti-Shirazi, “Design and Implementation of High Throughput, Robust, Parallel M-QAM Demodulator in Digital Communication Receivers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 8, pp. 1295–1304, 2016. View at Publisher · View at Google Scholar
  • Junxiu Liu, Jim Harkin, Liam P. Maguire, Liam J. McDaid, John J. Wade, and George Martin, “Scalable Networks-on-Chip Interconnected Architecture for Astrocyte-Neuron Networks,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 12, pp. 2290–2303, 2016. View at Publisher · View at Google Scholar
  • Liu Dongsheng, Liu Zilong, Li Lun, and Zou Xuecheng, “A Low-Cost Low-Power Ring Oscillator-based Truly Random Number Generator for Encryption on Smart Cards,” IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1–1, 2016. View at Publisher · View at Google Scholar
  • Honorio Martin, Pedro Peris-Lopez, Juan E. Tapiador, and Enrique San Millan, “A New TRNG Based on Coherent Sampling With Self-Timed Rings,” Ieee Transactions On Industrial Informatics, vol. 12, no. 1, pp. 91–100, 2016. View at Publisher · View at Google Scholar
  • Abdelkarim Cherkaoui, Lilian Bossuet, and Cedric Marchand, “Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators,” IEEE Transactions on Information Forensics and Security, vol. 11, no. 6, pp. 1291–1305, 2016. View at Publisher · View at Google Scholar
  • Siam U. Hussain, Mehrdad Majzoobi, and Farinaz Koushanfar, “A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators,” IEEE Transactions on Multi-Scale Computing Systems, vol. 2, no. 1, pp. 2–16, 2016. View at Publisher · View at Google Scholar
  • Fernando A. Escobar, Xin Chang, and Carlos Valderrama, “Suitability Analysis of FPGAs for Heterogeneous Platforms in HPC,” Ieee Transactions On Parallel And Distributed Systems, vol. 27, no. 2, pp. 600–612, 2016. View at Publisher · View at Google Scholar
  • Taimour Wehbe, and Xiaofang Wang, “Secure and Dependable NoC-Connected Systems on an FPGA Chip,” IEEE Transactions on Reliability, vol. 65, no. 4, pp. 1852–1863, 2016. View at Publisher · View at Google Scholar
  • Jihyuck Jo, Hoyoung Yoo, and In-Cheol Park, “Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 24, no. 2, pp. 754–758, 2016. View at Publisher · View at Google Scholar
  • Juan Antonio Clemente, Ruben Gran, Abel Chocano, Carlos del Prado, and Javier Resano, “Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 24, no. 2, pp. 530–543, 2016. View at Publisher · View at Google Scholar
  • Mario Garrido, Rikard Andersson, Fahad Qureshi, and Oscar Gustafsson, “Multiplierless Unity-Gain SDF FFTs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1–5, 2016. View at Publisher · View at Google Scholar
  • Fahimeh Jafari, Axel Jantsch, and Zhonghai Lu, “Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 12, pp. 3387–3400, 2016. View at Publisher · View at Google Scholar
  • Rui Yao, Jun Wu, Meiqun Wang, Xueyan Zhong, Ping Zhu, and Jiemei Liang, “State synchronization technique based on present input and healthy state for repairable TMR systems,” IEICE Electronics Express, 2016. View at Publisher · View at Google Scholar
  • Atef Ibrahim, Hamed Elsimary, and Abdullah Aljumah, “Novel Reconfigurable Hardware Accelerator for Protein Sequence Alignment Using Smith-Waterman Algorithm,” Ieice Transactions On Fundamentals Of Electronics Communications And Computer Sciences, vol. E99A, no. 3, pp. 683–690, 2016. View at Publisher · View at Google Scholar
  • Yung-Hao Lai, Yang-Lang Chang, Jyh-Perng Fang, Lena Chang, and Hirokazu Kobayashi, “Layer-Aware 3D-IC Partitioning for Area-Overhead Reduction Considering the Power of Interconnections and Pads,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E99.A, no. 6, pp. 1206–1215, 2016. View at Publisher · View at Google Scholar
  • Agees Kumar C., Sivarani T.S., and Joseph Jawhar S., “Intensive random carrier pulse width modulation for induction motor drives based on hopping between discrete carrier frequencies,” IET Power Electronics, 2016. View at Publisher · View at Google Scholar
  • George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, and Dionisios Pnevmatikatos, “Run-Time Management of Systems with Partially Reconfigurable FPGAs,” Integration, the VLSI Journal, 2016. View at Publisher · View at Google Scholar
  • Martin Kumm, and Peter Zipf, “Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”,” International Journal of Reconfigurable Computing, vol. 2016, pp. 1–3, 2016. View at Publisher · View at Google Scholar
  • Anatolij Sergiyenko, and Anastasia Serhienko, “Modules for Pipelined Mixed Radix FFT Processors,” International Journal of Reconfigurable Computing, vol. 2016, pp. 1–7, 2016. View at Publisher · View at Google Scholar
  • A. Al-Wattar, S. Areibi, and G. Grewal, “An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems,” International Journal of Reconfigurable Computing, vol. 2016, pp. 1–24, 2016. View at Publisher · View at Google Scholar
  • Muhammad Mazher Iqbal, Husain Parvez, and Muhammad Rashid, ““Multi-Circuit”: Automatic Generation of an Application Specific Configurable Core for Known Set of Application Circuits,” Journal of Circuits, Systems and Computers, vol. 25, no. 09, pp. 1650102, 2016. View at Publisher · View at Google Scholar
  • Matthew Mayhew, and Radu Muresan, “An overview of hardware-level statistical power analysis attack countermeasures,” Journal of Cryptographic Engineering, 2016. View at Publisher · View at Google Scholar
  • Fathollah Bistouni, and Mohsen Jahanshahi, “Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks,” Journal of Electronic Testing, 2016. View at Publisher · View at Google Scholar
  • Kohei Nagasu, Kentaro Sano, Fumiya Kono, and Naohito Nakasato, “FPGA-based tsunami simulation: Performance comparison with GPUs, and roofline model for scalability analysis,” Journal of Parallel and Distributed Computing, 2016. View at Publisher · View at Google Scholar
  • Rostam Affendi Hamzah, and Haidi Ibrahim, “Literature Survey on Stereo Vision Disparity Map Algorithms,” Journal of Sensors, vol. 2016, pp. 1–23, 2016. View at Publisher · View at Google Scholar
  • Marc Reichenbach, Max Kasparek, Konrad Häublein, Jan Niklas Bauer, Mohammad Alawieh, and Dietmar Fey, “Fast Heterogeneous Computing Architectures for Smart Antennas,” Journal of Systems Architecture, 2016. View at Publisher · View at Google Scholar
  • Camilo Sánchez-Ferreira, Jones Y. Mori, Mylène C. Q. Farias, and Carlos H. Llanos, “A real-time stereo vision system for distance measurement and underwater image restoration,” Journal of the Brazilian Society of Mechanical Sciences and Engineering, 2016. View at Publisher · View at Google Scholar
  • Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, and Habib Mehrez, “Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires,” Microprocessors And Microsystems, vol. 40, pp. 16–26, 2016. View at Publisher · View at Google Scholar
  • Pascal Cotret, Guy Gogniat, and Martha Johanna Sepulveda, “Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls,” Microprocessors and Microsystems, 2016. View at Publisher · View at Google Scholar
  • Sergio Saponara, and Luca Fanucci, “Configurable Network-on-Chip Router Macrocells,” Microprocessors and Microsystems, 2016. View at Publisher · View at Google Scholar
  • Khalid Javeed, Xiaojun Wang, and Mike Scott, “High performance hardware support for elliptic curve cryptography over general prime field,” Microprocessors and Microsystems, 2016. View at Publisher · View at Google Scholar
  • Omar Longoria-Gandara, Ramon Parra-Michel, Roberto Carrasco-Alvarez, and Eduardo Romero-Aguirre, “Iterative MIMO Detection and Channel Estimation Using Joint Superimposed and Pilot-Aided Training,” Mobile Information Systems, vol. 2016, pp. 1–11, 2016. View at Publisher · View at Google Scholar
  • Sandeep Pande, Fearghal Morgan, Finn Krewer, Jim Harkin, Liam McDaid, and Brian McGinley, “Rapid application prototyping for hardware modular spiking neural network architectures,” Neural Computing and Applications, 2016. View at Publisher · View at Google Scholar
  • Amritakar Mandal, Rajesh Mishra, and M. R. Nagar, “Implementation of complex digital PLL for phase detection in software defined radar,” Radioelectronics and Communications Systems, vol. 59, no. 4, pp. 151–162, 2016. View at Publisher · View at Google Scholar
  • Sascha Desmettre, Ralf Korn, Javier Varela, and Norbert Wehn, “Nested MC-Based Risk Measurement of Complex Portfolios: Acceleration and Energy Efficiency,” Risks, vol. 4, no. 4, pp. 36, 2016. View at Publisher · View at Google Scholar
  • D. Muralidharan, and R. Muthaiah, “Bus Based Synchronization Method for CHIPPER Based NoC,” Scientific Programming, vol. 2016, pp. 1–11, 2016. View at Publisher · View at Google Scholar
  • Ismail San, Nuray At, Ibrahim Yakut, and Huseyin Polat, “Efficient paillier cryptoprocessor for privacy-preserving data mining,” Security and Communication Networks, 2016. View at Publisher · View at Google Scholar
  • Muhammad Javed, Elyes Ben Hamida, and Wassim Znaidi, “Security in Intelligent Transport Systems for Smart Cities: From Theory to Practice,” Sensors, vol. 16, no. 6, pp. 879, 2016. View at Publisher · View at Google Scholar
  • Hilal Tayara, Woonchul Ham, and Kil Chong, “A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor,” Sensors, vol. 16, no. 12, pp. 2139, 2016. View at Publisher · View at Google Scholar
  • Felix Siegle, Tanya Vladimirova, Jorgen Ilstad, and Omar Emam, “Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications,” Acm Computing Surveys, vol. 47, no. 2, 2015. View at Publisher · View at Google Scholar
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  • Enrique Canto-Navarro, Mariano Lopez-Garcia, Rafael Ramos-Lara, and Raul Sanchez-Reillo, “Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 23, no. 11, pp. 2497–2507, 2015. View at Publisher · View at Google Scholar
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  • Tobias Kenter, Henning Schmitz, and Christian Plessl, “Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study,” International Journal of Reconfigurable Computing, vol. 2015, pp. 1–24, 2015. View at Publisher · View at Google Scholar