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Citations to this Journal [378 citations: 1–100 of 347 articles]

Articles published in International Journal of Reconfigurable Computing have been cited 378 times. The following is a list of the 347 articles that have cited the articles published in International Journal of Reconfigurable Computing.

  • Burhan Khurshid, “Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs,” Journal of Circuits, Systems and Computers, vol. 27, no. 01, pp. 1850002, 2018. View at Publisher · View at Google Scholar
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  • Miriam Guadalupe Cruz Jiménez, Uwe Meyer Baese, and Gordana Jovanovic Dolecek, “Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators,” EURASIP Journal on Advances in Signal Processing, vol. 2017, no. 1, 2017. View at Publisher · View at Google Scholar
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  • Reza Ramezani, Yasser Sedaghat, Mahmoud Naghibzadeh, and Juan Antonio Clemente, “Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms,” IEEE Transactions on Aerospace and Electronic Systems, pp. 1–1, 2017. View at Publisher · View at Google Scholar
  • Jingwei Hu, and Ray C. C. Cheung, “Toward Practical Code-Based Signature: Implementing Fast and Compact QC-LDGM Signature Scheme on Embedded Hardware,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 8, pp. 2086–2097, 2017. View at Publisher · View at Google Scholar
  • Felipe Tuyama De Faria Barbosa, Duarte Lopes De Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, and Jocemar Francisco De Souza Luciano, “Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 5, pp. 1064–1074, 2017. View at Publisher · View at Google Scholar
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  • Cesar Carranza, Daniel Llamocca, and Marios Pattichis, “Fast 2D Convolutions and Cross-Correlations Using Scalable Architectures,” IEEE Transactions on Image Processing, vol. 26, no. 5, pp. 2230–2245, 2017. View at Publisher · View at Google Scholar
  • Amin Yoosefi, and Hamid Reza Naji, “A Clustering Algorithm for Communication-Aware Scheduling of Task Graphs on Multi-Core Reconfigurable Systems,” IEEE Transactions on Parallel and Distributed Systems, vol. 28, no. 10, pp. 2718–2732, 2017. View at Publisher · View at Google Scholar
  • Carl Ingemarsson, Petter Kallstrom, Fahad Qureshi, and Oscar Gustafsson, “Efficient FPGA Mapping of Pipeline SDF FFT Cores,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2486–2497, 2017. View at Publisher · View at Google Scholar
  • Artjom Grudnitsky, Lars Bauer, and Jorg Henkel, “Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, pp. 594–607, 2017. View at Publisher · View at Google Scholar
  • Nuno M. C. Paulino, Joao Canas Ferreira, and Joao M. P. Cardoso, “Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 21–34, 2017. View at Publisher · View at Google Scholar
  • S. Santhosh Kumar, S. Vidhya, and M. M. Shanmugapriya, “Neural Network Architecture for Hybrid Network-On-Chip using Scalable Spiking for Man Machine Interface,” Indian Journal of Science and Technology, vol. 10, no. 16, pp. 1–7, 2017. View at Publisher · View at Google Scholar
  • Ulkuhan Guler, Ali Emre Pusane, and Günhan Dundar, “Design of efficient CMOS ring oscillator-based random number generator,” International Journal of Electronics, pp. 1–18, 2017. View at Publisher · View at Google Scholar
  • Chandrajit Pal, Pabitra Das, Amlan Chakrabarti, and Ranjan Ghosh, “Rician noise removal in magnitude MRI images using efficient anisotropic diffusion filtering,” International Journal of Imaging Systems and Technology, vol. 27, no. 3, pp. 248–264, 2017. View at Publisher · View at Google Scholar
  • Lekhobola Tsoeunyane, Simon Winberg, and Michael Inggs, “Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language,” International Journal of Reconfigurable Computing, vol. 2017, pp. 1–28, 2017. View at Publisher · View at Google Scholar
  • Justin A. Hogan, Raymond J. Weber, and Brock J. Lameres, “Reliability analysis of field-programmable gate-array-based space computer architectures,” Journal of Aerospace Information Systems, vol. 14, no. 4, pp. 247–258, 2017. View at Publisher · View at Google Scholar
  • Yulia Shichkina, and Alexander Koblov, “Reducing the Amount of Data for Creating Routes in a Dynamic DTN via Wi-Fi on the Basis of Static Data,” Journal of Computer Networks and Communications, vol. 2017, pp. 1–10, 2017. View at Publisher · View at Google Scholar
  • Lucian Petrica, “FPGA Optimized Cellular Automaton Random Number Generator,” Journal of Parallel and Distributed Computing, 2017. View at Publisher · View at Google Scholar
  • Syed Waqar Nabi, and Wim Vanderbauhede, “FPGA design space exploration for scientific HPC applications using a fast and accurate cost model based on roofline analysis,” Journal of Parallel and Distributed Computing, 2017. View at Publisher · View at Google Scholar
  • Bibin Johnson, Jiljo K. Moncy, and J. Sheeba Rani, “Self adaptable high throughput reconfigurable bilateral filter architectures for real-time image de-noising,” Journal of Real-Time Image Processing, 2017. View at Publisher · View at Google Scholar
  • Mário Saldanha, Bruno Zatt, Luciano Agostini, Gustavo Sanchez, and Marcelo Porto, “Energy-aware scheme for the 3D-HEVC depth maps prediction,” Journal of Real-Time Image Processing, vol. 13, no. 1, pp. 55–69, 2017. View at Publisher · View at Google Scholar
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  • Renato Coral Sampaio, José Maurício S. T. Motta, and Carlos Humberto Llanos, “An FPGA-based controller design for a five degrees of freedom robot for repairing hydraulic turbine blades,” Journal of the Brazilian Society of Mechanical Sciences and Engineering, 2017. View at Publisher · View at Google Scholar
  • Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, and Muhammad N. Marsono, “Ping-lock round robin arbiter,” Microelectronics Journal, vol. 63, pp. 81–93, 2017. View at Publisher · View at Google Scholar
  • Atef Dorai, Virginie Fresse, El-Bay Bourennane, Catherine Combes, and Abdellatif Mtibaa, “A collision management structure for NoC deployment on multi-FPGA,” Microprocessors and Microsystems, vol. 49, pp. 28–43, 2017. View at Publisher · View at Google Scholar
  • Johanna Sepulveda, Daniel Flórez, Vincent Immler, Guy Gogniat, and Georg Sigl, “Efficient Security Zones Implementation through Hierarchical Group Key Management at NoC-Based MPSoCs,” Microprocessors and Microsystems, 2017. View at Publisher · View at Google Scholar
  • Alireza Monemi, Jia Wei Tang, Maurizio Palesi, and Muhammad N. Marsono, “ProNoC: A Low Latency Network-on-Chip based Many-Core System-on-Chip Prototyping Platform,” Microprocessors and Microsystems, 2017. View at Publisher · View at Google Scholar
  • Lei Wan, Junxiu Liu, Jim Harkin, Liam McDaid, and Yuling Luo, “Layered Tile Architecture for Efficient Hardware Spiking Neural Networks,” Microprocessors and Microsystems, 2017. View at Publisher · View at Google Scholar
  • Sarah Hachemi-Benziane, and Abdelkader Benyettou, “On the influence of anisotropic diffusion filter on dorsal hand authentication using eigenveins,” Multidimensional Systems and Signal Processing, 2017. View at Publisher · View at Google Scholar
  • Akram Reza, “Online multi-application Mapping in photonic Network-on-Chip with mesh topology,” Optical Switching and Networking, 2017. View at Publisher · View at Google Scholar
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  • Julian Oppermann, Lukas Sommer, and Andreas Koch, “SpExSim: assessing kernel suitability for C-based high-level hardware synthesis,” The Journal of Supercomputing, 2017. View at Publisher · View at Google Scholar
  • Mostafa Chakir, Hicham Akhamal, and Hassan Qjidaa, “A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor,” The Scientific World Journal, vol. 2017, pp. 1–15, 2017. View at Publisher · View at Google Scholar
  • Adesh Kumar, Gaurav Verma, and Mukul Kumar Gupta, “FM Receiver Design Using Programmable PLL,” Wireless Personal Communications, 2017. View at Publisher · View at Google Scholar
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  • Bernd Bischl, Pascal Kerschke, Lars Kotthoff, Marius Lindauer, Yuri Malitsky, Alexandre Fréchette, Holger Hoos, Frank Hutter, Kevin Leyton-Brown, Kevin Tierney, and Joaquin Vanschoren, “ASlib: A benchmark library for algorithm selection,” Artificial Intelligence, vol. 237, pp. 41–58, 2016. View at Publisher · View at Google Scholar
  • M. Antonelli, L. De Micco, and H.A. Larrondo, “Measuring the Jitter of Ring Oscillators by means of Information Theory Quantifiers,” Communications in Nonlinear Science and Numerical Simulation, 2016. View at Publisher · View at Google Scholar
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  • Gavin Vaz, Heinrich Riebler, Tobias Kenter, and Christian Plessl, “Potential and methods for embedding dynamic offloading decisions into application code,” Computers & Electrical Engineering, 2016. View at Publisher · View at Google Scholar
  • Y.H. Moon, I.K. Eom, and S.H. Cheon, “Fast descriptor extraction method for a SURF-based interest point,” Electronics Letters, 2016. View at Publisher · View at Google Scholar
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  • Michał Kierzynka, Lars Kosmann, Micha vor dem Berge, Stefan Krupop, Jens Hagemeyer, René Griessl, Meysam Peykanu, and Ariel Oleksiak, “Energy efficiency of sequence alignment tools—Software and hardware perspectives,” Future Generation Computer Systems, 2016. View at Publisher · View at Google Scholar
  • Vafa Andalibi, Francois Christophe, Teemu Laukkarinen, and Tommi Mikkonen, “Effective Connectivity Analysis in Brain Networks: A GPU-Accelerated Implementation of the Cox Method,” IEEE Journal of Selected Topics in Signal Processing, vol. 10, no. 7, pp. 1226–1237, 2016. View at Publisher · View at Google Scholar
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  • Mehdi Ayat, Sattar Mirzakuchaki, and AliAsghar Beheshti-Shirazi, “Design and Implementation of High Throughput, Robust, Parallel M-QAM Demodulator in Digital Communication Receivers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 8, pp. 1295–1304, 2016. View at Publisher · View at Google Scholar
  • Liu Dongsheng, Liu Zilong, Li Lun, and Zou Xuecheng, “A Low-Cost Low-Power Ring Oscillator-based Truly Random Number Generator for Encryption on Smart Cards,” IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1–1, 2016. View at Publisher · View at Google Scholar
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