El&#237;as Todorovich

Valentin Obac Roda

Selected Papers from SPL 2009: Programmable Logic and Applications


Reconfigurable Computers (RCs) with hardware (FPGA) co-processors
can achieve significant performance improvement compared with
traditional microprocessor (<svg style="vertical-align:-3.56265pt;width:20.375px;" id="M1" height="15.6125" version="1.1" viewBox="0 0 20.375 15.6125" width="20.375" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.017,-0,0,-.017,.062,11.112)"><path id="x1D707" d="M538 96q-38 -45 -84 -76.5t-71 -31.5q-44 0 -15 117q12 49 18 89h-2q-99 -128 -163 -178q-36 -28 -70 -28q-26 0 -44 38h-2q-16 -69 -16 -129q0 -43 11 -75.5t24 -42.5l1 -6q-7 -12 -24.5 -23t-37.5 -11q-40 0 -40 76q0 52 35 202l94 407l78 24l5 -5q-32 -122 -72 -310&#xA;q-7 -33 0 -55t25 -22q36 0 105.5 75t107.5 145l32 146l75 26h10q-50 -197 -78 -347q-7 -38 6 -38q7 0 31 17t47 39z" /></g><g transform="matrix(.017,-0,0,-.017,9.497,11.112)"><path id="x1D443" d="M619 482q0 -69 -40.5 -119t-96 -72.5t-118.5 -26.5h-44l-70 20l-31 -151q-14 -67 0.5 -83t89.5 -22l-5 -28h-287l8 28q65 7 81.5 22t29.5 83l79 398q12 56 0.5 70.5t-78.5 20.5l7 28h255q108 0 164 -43t56 -125zM524 478q0 141 -146 141q-25 0 -47 -8q-16 -6 -20.5 -13.5&#xA;t-10.5 -39.5l-43 -241q37 -13 83 -13q67 0 125.5 45t58.5 129z" /></g></svg>)-based computers for many
scientific applications. The potential amount of speedup depends on the intrinsic parallelism of the target application
as well as the characteristics of the target platform. In this work,
we use image processing applications as a case study to demonstrate
how hardware designs are parameterized by the co-processor
architecture, particularly the data I/O, i.e., the local memory of the FPGA device and the interconnect
between the FPGA and the <svg style="vertical-align:-3.56265pt;width:20.375px;" id="M2" height="15.6125" version="1.1" viewBox="0 0 20.375 15.6125" width="20.375" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.017,-0,0,-.017,.062,11.112)"><use xlink:href="#x1D707" /></g><g transform="matrix(.017,-0,0,-.017,9.497,11.112)"><use xlink:href="#x1D443" /></g></svg>. The local memory has to be used by applications that access data randomly. A typical case
belonging to this category is image registration. On the other hand,
an application such as edge detection can directly read data through the
interconnect in a sequential fashion. Two different algorithms of
image registration, the exhaustive search algorithm and the Discrete
Wavelet Transform (DWT)-based search algorithm, are implemented on
hardware, i.e., Xilinx Vertex-IIPro 50 on the Cray XD1 reconfigurable computer. The
performance improvements of hardware implementations are <svg style="vertical-align:-0.1638pt;width:33.974998px;" id="M3" height="11.125" version="1.1" viewBox="0 0 33.974998 11.125" width="33.974998" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.017,-0,0,-.017,.062,10.862)"><path id="x31" d="M384 0h-275v27q67 5 81.5 18.5t14.5 68.5v385q0 38 -7.5 47.5t-40.5 10.5l-48 2v24q85 15 178 52v-521q0 -55 14.5 -68.5t82.5 -18.5v-27z" /></g><g transform="matrix(.017,-0,0,-.017,8.222,10.862)"><path id="x30" d="M241 635q53 0 94 -28.5t63.5 -76t33.5 -102.5t11 -116q0 -58 -11 -112.5t-34 -103.5t-63.5 -78.5t-94.5 -29.5t-95 28t-64.5 75t-34.5 102.5t-11 118.5q0 58 11.5 112.5t34.5 103t64.5 78t95.5 29.5zM238 602q-32 0 -55.5 -25t-35.5 -68t-17.5 -91t-5.5 -105&#xA;q0 -76 10 -138.5t37 -107.5t69 -45q32 0 55.5 25t35.5 68.5t17.5 91.5t5.5 105t-5.5 105.5t-18 92t-36 68t-56.5 24.5z" /></g><g transform="matrix(.017,-0,0,-.017,20.155,10.862)"><path id="xD7" d="M528 54l-36 -38l-198 201l-198 -201l-36 38l197 200l-197 201l36 38l198 -202l198 202l36 -38l-197 -201z" /></g></svg> and <svg style="vertical-align:-0.0pt;width:25.8125px;" id="M4" height="10.9125" version="1.1" viewBox="0 0 25.8125 10.9125" width="25.8125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.017,-0,0,-.017,.062,10.862)"><path id="x32" d="M412 140l28 -9q0 -2 -35 -131h-373v23q112 112 161 170q59 70 92 127t33 115q0 63 -31 98t-86 35q-75 0 -137 -93l-22 20l57 81q55 59 135 59q69 0 118.5 -46.5t49.5 -122.5q0 -62 -29.5 -114t-102.5 -130l-141 -149h186q42 0 58.5 10.5t38.5 56.5z" /></g><g transform="matrix(.017,-0,0,-.017,11.996,10.862)"><use xlink:href="#xD7" /></g></svg>, respectively. Regarding the category of applications that
directly access the interconnect, the hardware implementation of Canny edge detection can achieve <svg style="vertical-align:-0.1638pt;width:42.137501px;" id="M5" height="11.075" version="1.1" viewBox="0 0 42.137501 11.075" width="42.137501" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.017,-0,0,-.017,.062,10.8)"><path id="x35" d="M153 550l-26 -186q79 31 111 31q90 0 141.5 -51t51.5 -119q0 -93 -89 -166q-85 -69 -173 -71q-32 0 -61.5 11.5t-41.5 23.5q-18 17 -17 34q2 16 22 33q14 9 26 -1q61 -50 124 -50q60 0 93 43.5t33 104.5q0 69 -41.5 110t-121.5 41q-53 0 -102 -20l38 305h286l6 -8&#xA;l-26 -65h-233z" /></g><g transform="matrix(.017,-0,0,-.017,8.222,10.8)"><path id="x34" d="M456 178h-96v-72q0 -51 12.5 -62.5t72.5 -16.5v-27h-256v27q65 5 78 17t13 62v72h-260v28q182 271 300 426h40v-407h96v-47zM280 225v295h-2q-107 -148 -196 -295h198z" /></g><g transform="matrix(.017,-0,0,-.017,16.381,10.8)"><use xlink:href="#x34" /></g><g transform="matrix(.017,-0,0,-.017,28.314,10.8)"><use xlink:href="#xD7" /></g></svg> speedup.

Miaoqing Huang

Olivier Serres

Tarek El-Ghazawi

Gregory Newby

Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.

Ludovic Devaux

Sana Ben Sassi

Sebastien Pillement

Daniel Chillet

Didier Demigny

Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures

This paper presents the design and implementation on FPGA devices of an algorithm for computing similarities between neighboring frames in a video sequence using luminance information. By taking advantage of the well-known flexibility of Reconfigurable Logic Devices, we have designed a hardware implementation of the algorithm used in video segmentation and indexing. The experimental results show the tradeoff between concurrent sequential resources and the functional blocks needed to achieve maximum operational speed while achieving minimum silicon area usage. To evaluate system efficiency, we compare the performance of the hardware solution to that of calculations done via software using general-purpose processors with and without an SIMD instruction set.

Sergio R. Geninatti

Jos&#233; Ignacio Benavides Ben&#237;tez

Manuel Hern&#225;ndez Calvi&#241;o

Nicol&#225;s Guil Mata

Concurrent Calculations on Reconfigurable Logic Devices Applied to the Analysis of Video Images

Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this
situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to
resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs,
hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07&#37; while increasing the number of CLBs by 13.28&#37; compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89&#37;.

Hanyu Liu

Ali Akoglu

Timing-Driven Nonuniform Depopulation-Based Clustering

This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the <i>P</i> and <i>G</i> functions for carry-chain optimization purposes. Several alternative designs are presented. Then, attention is given to FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. Better time delays have been registered for decimal numbers within the same range of operands.

G. Bioul

M. Vazquez

J. P. Deschamps

G. Sutter

High-Speed FPGA 10's Complement Adders-Subtractors

This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs) that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.

Tobias Becker

Peter Jamieson

Wayne Luk

Peter Y. K. Cheung

Tero Rissa

Power Characterisation for Fine-Grain Reconfigurable Fabrics

A technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop under hardware size constraints. The approach is demonstrated using three applications: speech recognition, image processing, and the N-Body problem. Experimental results show that a maximum speedup of 34 is achieved on a 274 MHz FPGA for the N-Body over a 2.6 GHz microprocessor, which is 4.1 times higher than that of an approach without unrolling.

Yuet Ming Lam

José Gabriel F. Coutinho

Chun Hok Ho

Philip Heng Wai Leong

Multiloop Parallelisation Using Unrolling and Fission

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International Journal of Reconfigurable Computing

Selected Papers from SPL 2009 Programmable Logic and Applications

Selected Papers from SPL 2009 Programmable Logic and Applications

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