A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm

Pseudocode 1

clk_count = 0; // count the number of rising edges for

the external clock (array_clk in Figure 4).

hits_vector; //register which holds bits from outputs of

16 3-input AND gates.

IF (array_clk’event and array_array_clk = “1”) THEN

//external clock rising edge

 IF (clk_count < = 15) then

  IF (clk_count < 15) then

   IF (hits_vector (clk_count) = “1”) then

    Record the hit location in the query and subject

    sequence;

    clk_count = clk_count +1;

   ELSE

    clk_count = clk_count +1;

   END IF;

  ELSE

    IF (hits_vector (clk_count) = “1”) then

     Record the hit location in the query and subject

     sequence;

    ELSE

     clk_count = 0;

    END IF;

   END IF;

  END IF;

END IF;