A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm

Table 1

Synthesis performance comparison between tree-BLAST and ours.

	Our architecture			Tree-BLAST
FPGA	XC5VLX110T	XC2VP70	XC4VLX160	XC2VP70	XC4VLX160
Array size	2048	2048	2048	600	1024
Slice (%)	55	87	59.2	—	78
Memory (%)	20.3	42	28	—	88
Clock (MHz)	136	145	158	110	178