Table of Contents
ISRN Electronics
Volume 2012, Article ID 435209, 15 pages
Research Article

High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver

Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka 1000, Bangladesh

Received 7 September 2012; Accepted 24 September 2012

Academic Editors: S. Gift, S. Hall, and P. Wachulak

Copyright © 2012 Apratim Roy. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A new microwave receiver configuration which transmits reference pulses embedded in data streams for synchronization is analyzed with a 90-nm IBM CMOS standard. A two-stage cascode low-noise amplifier (LNA) is proposed for the receiver front-end which is matched by a passive network to save on power-expensive matching techniques. The amplifier exploits a double-differential topology and achieves a below 4 dB noise figure near the center frequency. The overall 3-dB bandwidth is 3.3 GHz with peaking up to 20.5 dB in the -band. The back-end of the receiver is implemented through an adjustable analog window-detection circuit. It avoids the use of control voltage generators and sample-hold (S/H) blocks to save electronic overhead and is simulated with a 0.1~2.0 Gbps pulse stream. The achieved speed-to-power ratio for the back-end has a maximum limit of 266 GHz/W. When compared against simulated results of published literature, the proposed designs show improved performance in terms of small-signal gain, noise, speed, and power dissipation.