Table of Contents
ISRN Electronics
Volume 2012, Article ID 529194, 7 pages
Research Article

Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits

1Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, India
2Department of Electronics and Communication Engineering, Netaji Subhash Institute of Technology, New Delhi 110078, India

Received 21 September 2012; Accepted 31 October 2012

Academic Editors: A. Mercha and I. Shubin

Copyright © 2012 Kirti Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented.