International Scholarly Research Notices / 2012 / Article / Fig 3

Research Article

Barrier Evaluation by Linearly Increasing Voltage Technique Applied to Si Solar Cells and Irradiated Pin Diodes

Figure 3

(a) Simulated BELIV currents 𝑖 𝐢 ( 𝑑 ) for a diode with 𝐢 𝑏 0 = 7 0 p F , calculated without delay (solid curve) and using convolution integral with 𝑅 𝐢 values of 𝑅 𝐢 = 2  ns (dot), 𝑅 𝐢 = 2 0  ns (dash), and 𝑅 𝐢 = 2 0 0  ns (dash-dot). (b) Simulated time-dependent voltage drops on load resistor ( 𝑅 𝐿 = 5 0  Ω) and on capacitor ( 𝐢 = 4 3 0  pF) for LIV pulse of 𝜏 𝑃 𝐿 = 1 πœ‡ 𝑠 of a peak voltage π‘ˆ 𝑃 = 8 V and the BELIV transients simulated by using (1) and (2) ( black symbol + line), by using (1) and (4) (gray line), and analytic solutions with 𝑅 𝐢 = 2 0 n s (1) and (3) (black line). (c) Numerically simulated BELIV voltage transients π‘ˆ 𝑅 βˆ— ( 𝑑 ) as a function of an LIV pulse peak voltage π‘ˆ 𝑃 compared with those simulated by analytical approximation. (d) Numerically simulated BELIV voltage transients π‘ˆ 𝑅 βˆ— ( 𝑑 ) as a function of initial barrier capacitance values 𝐢 𝑏 0 compared with those simulated by analytical approximation.
543790.fig.003a
(a)
543790.fig.003b
(b)
543790.fig.003c
(c)
543790.fig.003d
(d)

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