Table of Contents
ISRN Nanotechnology
Volume 2012, Article ID 689023, 35 pages
Review Article

Advanced CMOS Gate Stack: Present Research Progress

1Department of Electrical and Electronic Engineering, Xi’an Jiaotong-Liverpool University, Suzhou, Jiangsu 215123, China
2Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3GJ, UK
3Department of Materials Science and Engineering, University of Liverpool, Liverpool L69 3GH, UK

Received 6 September 2011; Accepted 29 September 2011

Academic Editors: M. Cazzanelli and K. Yong

Copyright © 2012 Chun Zhao et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor technology require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k). When the SiO2 gate thickness is reduced below 1.4 nm, electron tunneling effects and high leakage currents occur which present serious obstacles for device reliability. In recent years, various alternative gate dielectrics have been researched. Following the introduction of HfO2 into the 45 nm process by Intel in 2007, the screening and selection of high-k gate stacks, understanding their properties, and their integration into CMOS technology have been a very active research area. This paper reviews the progress and efforts made in the recent years for high-k dielectrics, which can be potentially integrated into 22 nm (and beyond) technology nodes. Our work includes deposition techniques, physical characterization methods at the atomic scale, and device reliability as the focus. For most of the materials discussed here, structural and physical properties, dielectric relaxation issues, and projections towards future applications are also discussed.