Single OTRA Based Analog Multiplier and Its Applications

Abstract

This paper presents an analog multiplier using single operational transresistance amplifier (OTRA). The proposed circuit is suitable for integration as it does not use any external passive component. It can be used as a four-quadrant multiplier. Theoretical propositions are verified through PSPICE simulations using 0.5 μm CMOS parameters provided by MOSIS (AGILENT). The simulation results are in close agreement with theoretical predictions. The workability of the proposed multiplier is also tested through two applications, namely, a squarer and an amplitude modulator.

1. Introduction

Analog multipliers find extensive application in the field of telecommunication, control, instrumentation, measurement, and signal processing [1]. A number of circuits are reported in literature relating to analog multipliers [1–12]. Circuits presented in [2–7] are based on Gilbert multiplier [12] and are suitable for CMOS integrated technology. The other class of the circuits is implemented using active analog blocks such as operational transconductance amplifier [1], differential difference current conveyors [8], current feedback amplifiers [9], current-controlled current conveyor [10], and current difference buffered amplifier [11].

Recently the OTRA has emerged as an alternate analog building block [13–26] which inherits all the advantages of current mode techniques. The OTRA is a high gain current input voltage output device. The input terminals of OTRA are internally grounded, thereby eliminating response limitations due to parasitic capacitances and resistances [13] at the input. Several high performance CMOS OTRA topologies have been proposed in the literature [13–16]. In the recent past OTRA has been extensively used as an analog building block for realizing a number of analog signal processing [17–21] and generation circuits [22–24]. This paper presents a single OTRA based low voltage analog multiplier which does not use any external passive components and hence is suitable for integration. The proposed circuit can be used as a four quadrant multiplier without any change of topology. The workability of the proposed multiplier is demonstrated through two applications, namely, a squarer and an amplitude modulator.

2. The Proposed Multiplier Circuit

2.1. OTRA

OTRA is a three-terminal device, shown symbolically in Figure 1 and its port relations are characterized by the following matrix: 𝑉_𝑝𝑉_𝑛𝑉_𝑂=𝑅000000_𝑚−𝑅_𝑚0𝐼_𝑝𝐼_𝑛𝐼_𝑂, (1) where 𝑅_𝑚 is transresistance gain of OTRA. For ideal operations 𝑅_𝑚 approaches infinity and forces the input currents to be equal. Thus OTRA must be used in a negative feedback configuration.

Figure 1 

OTRA circuit symbol.

Figure 2 Shows the CMOS realization of OTRA [15] which consists of the cascaded connection of the modified differential current conveyor (MDCC) [8] and common source amplifier. MDCC performs the current differencing operation and forces the two input terminals to be virtually grounded whereas the common source amplifier provides high gain.

Figure 2 

Figure 6 CMOS implementation of OTRA [15].

2.2. Basic Multiplier Circuit

Figure 3 Shows OTRA based multiplier structure. The transistors M₁, M₂,  M₃, and M₄ are matched transistors and operate in the linear region. In this paper 𝑣₁ and 𝑣₂ represent small signals, whereas 𝑉_𝐶1, 𝑉_𝐶2, and 𝑉_DC are the bias voltages. OTRA inputs keep the sources of the two transistors M₁ and M₂ virtually grounded. The drain current for the MOS transistor operating in triode region is given by [27] 𝐼_𝐷𝑊=𝑘𝐿𝑉_GS−𝑉_𝑇−𝑉_DS2𝑉_DS, (2) where 𝑘 is transconductance; 𝑊 and 𝐿 respectively represent the channel width and length of the of the MOSFET. The other terms have their usual meaning.

Figure 3 

Proposed OTRA based multiplier structure.

Using (2) the currents through 𝑝 and 𝑛 terminals of OTRA, that is, 𝑖_𝑝 and 𝑖_𝑛, respectively, can be expressed as 𝑖_𝑝=𝐾_𝑛𝑊𝐿𝑉_DC+𝑣₁−𝑉_𝑇−𝑣₂2𝑣₂+𝐾_𝑛𝑊𝐿𝑉_𝐶1−𝑉_𝑇−𝑣_𝑜2𝑣_𝑜,𝑖_𝑛=𝐾_𝑛𝑊𝐿𝑉_DC−𝑉_𝑇−𝑣₂2𝑣₂+𝐾_𝑛𝑊𝐿𝑉_𝐶2−𝑉_𝑇−𝑣_𝑜2𝑣_𝑜. (3)(4) As 𝑅_𝑚 approaches infinity the input currents are forced to be equal resulting in 𝑣_𝑜=𝑣₁𝑣₂𝑉_𝐶2−𝑉_𝐶1=𝐾𝑣₁𝑣₂, (5) where 𝐾 is a proportionality constant and is the inverse of difference of gate voltages of M₃ and M₄.

2.3. Implementation Scheme for Superimposition of a Small Signal on DC Bias

As can be seen from Figure 3 the gate voltage of M₁ is (𝑉_DC+𝑣₁) which is a small signal superimposed over a dc bias. This voltage addition can be implemented using a scheme proposed in Figure 4 wherein 𝑣_𝑥 is a small signal voltage and 𝑉_𝐶 is a bias voltage.

Figure 4 

Scheme for implementing an ac superimposed on dc bias.

If M_𝑃1 and M_𝑃2 are matched transistors and are operating in saturation then their drain currents will be equal resulting in 12𝐾_𝑝𝑊𝐿𝑣−𝑉_𝐶−𝑉_𝑡𝑝²=12𝐾_𝑝𝑊𝐿𝑣_𝑥−𝑣−𝑉_𝑡𝑝², (6) which gives 𝑉𝑣=^𝐶+𝑣_𝑥2. (7)

The voltage given by (7) can be used as the gate voltage for transistor M₁ of Figure 3. Similarly gate voltage for transistor M₂ can be obtained from (7) by making 𝑣_𝑥=0. Substituting these values of gate voltages in (5) the output of the multiplier gets modified to 𝑣_𝑜=𝐾^′𝑣₁𝑣₂,where𝐾^′=𝐾2. (8)

2.4. The Proposed MOS Based Multiplier Structure

The complete MOS based multiplier structure is depicted in Figure 5 which incorporates the voltage addition scheme of Figure 4.

Figure 5 

Complete multiplier circuit.

As the transistors M₁, M₂, M₃, and M₄ need to operate in the triode region for proper operation of the multiplier the following conditions should be satisfied: 𝑉_𝐶+𝑣₁2−𝑉_𝑡𝑛>𝑣₂,𝑉_𝐶2−𝑉_𝑡𝑛>𝑣₂,𝑉_𝐶1−𝑉_𝑡𝑛>𝑣_𝑜,𝑉_𝐶2−𝑉_𝑡𝑛>𝑣_𝑜. (9)

Now using (7) along with (9) the conditions for input signals 𝑣₁ and 𝑣₂ can be computed as 𝑉_𝑡𝑝<𝑣₁<𝑉_𝐶+2𝑉_𝑡𝑝,𝑣₂<𝑉_𝐶+𝑣₁2−𝑉_𝑡𝑛. (10)

These equations suggest that the dynamic input range of the multiplier is controlled by 𝑉_𝐶.

3. Nonideal Analysis

In this section the effect of finite transresistance gain of OTRA on multiplier is considered and compensation is employed for high frequency applications. Ideally the transresistance gain 𝑅_𝑚 is assumed to approach infinity. However, practically 𝑅_𝑚 is a frequency dependent finite value [13]. Considering a single pole model for the transresistance gain, 𝑅_𝑚 can be expressed as 𝑅_𝑚(𝑠)=𝑅₀1+𝑠/𝜔₀. (11)

For high frequency applications the transresistance gain 𝑅_𝑚(𝑠) reduces to 𝑅_𝑚(𝑠)≈1𝑠𝐶_𝑝,where𝐶_𝑝=1𝑅₀𝜔₀. (12)

For high frequency applications the effect of transistor capacitances needs to be considered. Taking this effect into account the currents 𝑖_𝑝 given by (3) modifies to 𝑖_𝑝=𝐾_𝑛𝑊𝐿𝑉_DC+𝑣₁−𝑉_𝑇−𝑣₂2𝑣₂+𝐾_𝑛𝑊𝐿𝑉_𝐶1−𝑉_𝑇−𝑣_𝑜2𝑣_𝑜+𝑣₁𝑠𝐶_gs1, (13) where 𝐶_gs1 is the gate to source capacitance of M₁; however, the current 𝑖_𝑛 remains the same as (4). The effect of 𝐶_gs1 can be compensated by adding a MOSFET M₉, operating in triode region, at the inverting terminal of OTRA as shown in Figure 6. The effective gate to source capacitance of M₉ should be equal to 𝐶_gs1. This would result in 𝑖_𝑛 as 𝑖_𝑛=𝐾_𝑛𝑊𝐿𝑉_DC−𝑉_𝑇−𝑣₂2𝑣₂+𝐾_𝑛𝑊𝐿𝑉_𝐶2−𝑉_𝑇−𝑣_𝑜2𝑣_𝑜+𝑣₁𝑠𝐶_gs1. (14)

Figure 6 

Complete multiplier circuit with 𝐶gs compensation of transistor M1.

The third term in (14) results due to gate to source capacitance of M₉.

Substituting (12), (13), and (14) in (1), 𝑣_𝑜, the output of multiplier can be evaluated as 𝑣_𝑜=𝑣₁𝑣₂/𝑉_𝐶2−𝑉_𝐶11+𝑠𝐶_𝑝/𝐾_𝑛(𝑊/𝐿)𝑉_𝐶2−𝑉_𝐶1. (15)

And hence the 3 dB bandwidth of the multiplier can be expressed as 𝐾_𝑛(𝑊/𝐿)𝑉_𝐶2−𝑉_𝐶1𝐶_𝑝. (16)

4. Simulation Results

The performance of the proposed multiplier of Figure 5 is verified through SPICE simulation using 0.5 μm CMOS process parameters provided by MOSIS (AGILENT). CMOS implementation of the OTRA [15] shown in Figure 2 is used and supply voltages are taken as ±1.5 V. Aspect ratios used for different transistors of OTRA are the same as in [15] and are given in Table 1. All the transistors M₁–M₈ were used with equal aspect ratios having 𝑊/𝐿=1𝜇/0.5𝜇. Control voltage is taken as 𝑉_𝐶=2 V, 𝑉_𝐶1=1 V, and 𝑉_𝐶2=1.25 V.

Table 1 

Aspect ratio of the transistors in OTRA circuit.

Figure 7 depicts the dc transfer characteristics of the proposed multiplier. The transfer curve 𝑣_𝑜 versus 𝑣₁, with 𝑣₂ kept constant at 250 mV, is shown in Figure 7(a). It is observed that 𝑣_𝑜 varies almost linearly with 𝑣₁. The nonlinearity curve representing maximum percent deviation of the ideal transfer characteristic as a function of input voltage 𝑣₁ is shown in Figure 7(b). It is observed that the maximum nonlinearity over the entire input range does not exceed 2.05%. In Figure 7(c)𝑣_𝑜 is plotted with respect to 𝑣₁ for different values of 𝑣₂. Voltage 𝑣₁ is swept from −300 mV to 300 mV while 𝑣₂ is varied from −150 mV to 150 mV in steps of 50 mV. It shows that the proposed circuit is a four-quadrant multiplier.

(a) 𝑣𝑜 versus 𝑣1 with 𝑣2=250 mV

(b) Nonlinearity curve with 𝑣2=250 mV

(c) 𝑣𝑜 versus 𝑣1 when 𝑣2 is varied from −150 mV to 150 mV

Figure 7 

DC transfer characteristic.

The frequency response of the proposed multiplier is shown in Figure 8 for which 𝑣₁ is kept constant at 200 mV whereas 𝑣₂ is taken as an ac source having amplitude 250 mV. The 3 dB bandwidth is found to be 8 MHz.

Figure 8 

AC characteristic of the proposed multiplier.

Figure 9 shows the total harmonic distortion (THD) as a function of input signal amplitude when a constant dc voltage (250 mV) is applied to 𝑣₂ while a 1 KHz sinusoidal signal is applied to 𝑣₁ with varying amplitude. It can be seen that the maximum THD remains under 0.2% for the entire input range. Total power consumption of the proposed multiplier is 0.83 mw when 𝑣₁=𝑣₂=0 V, 𝑉_𝐶=2 V, 𝑉_𝐶1=1 V, and 𝑉_𝐶2=1.25 V.

Figure 9 

THD versus input signal amplitude.

5. Applications

5.1. Squarer

The proposed multiplier can be used as a squarer circuit if 𝑣₁=𝑣₂=𝑣_in. The output of the multiplier is given by 𝑣_𝑜=𝐾^′𝑣²_in. (17)

Figure 10 shows the square transfer characteristics wherein 𝑣_in is varied from −400 mV to 400 mV.

Figure 10 

Square transfer characteristics.

The observed output of the squarer is shown in Figure 11. The input signal is taken as a 300 mV, 500 KHz sinusoid. The squared output is shown in Figure 11(a) and the spectrum of the squared output is shown in Figure 11(b).

(a) Time domain output of the squarer

(b) Spectrum of squared sine wave

Figure 11 

Output of the squarer.

5.2. Amplitude Modulator

The proposed multiplier, being a four-quadrant multiplier, can be used as an amplitude modulator (AM). A 5 KHz signal with 200 mV amplitude is multiplied by 250 mV, 50 KHz signal. Figure 12 shows the output of the proposed multiplier confirming the modulation function. The time domain response of the multiplier is shown in Figures 12(a) and 12(b) displays the frequency spectrum.

(a) Time domain response

(b) Frequency spectrum

Figure 12 

Multiplication of two sinusoids.

6. Conclusion

A single OTRA based analog multiplier is proposed which can be used as a four-quadrant multiplier also. The circuit does not require any passive element thus making it suitable for integration. Its application as a squarer and an amplitude modulator is also discussed. Theoretical propositions are verified through PSPICE simulations using 0.5 μm CMOS parameters provided by MOSIS (AGILENT). Various performance parameters are analyzed through simulations and are found in close agreement to theoretical predictions.