Table of Contents
ISRN Electronics
Volume 2013 (2013), Article ID 271316, 7 pages
http://dx.doi.org/10.1155/2013/271316
Research Article

Leakage Power Analysis of Domino XOR Gate

Department of Electronics and Communication, M.N.N.I.T, Allahabad 211004, India

Received 23 November 2012; Accepted 13 December 2012

Academic Editors: M. Hopkinson and V. McGahay

Copyright © 2013 A. K. Pandey et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.