Research Article
Leakage Power Analysis of Domino XOR Gate
Table 3
Leakage power consumption (μW) of four XOR circuits in different Input States and Clock States at 110°C.
| Inputs | DXN | DXP | DXHL | DXHD | CLK = 0 | CLK = 1 | CLK = 0 | CLK = 1 | CLK = 0 | CLK = 1 | CLK = 0 | CLK = 1 |
| , | 14.87 | 21.22 | 16.81 | 14.72 | 6.05 | 13.04 | 5.55 | 1.34 | , | 19.07 | 17.78 | 16.94 | 14.41 | 8.30 | 15.66 | 7.85 | 1.88 | , | 16.11 | 17.58 | 16.46 | 13.08 | 8.30 | 15.66 | 7.85 | 1.68 | , | 14.55 | 21.37 | 18.02 | 15.93 | 9.04 | 10.63 | 8.57 | 10.22 |
|
|