Table of Contents
ISRN Electronics
Volume 2013 (2013), Article ID 376869, 8 pages
Research Article

A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

1Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran 1477893855, Iran
2Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran 37541-374, Iran
3Department of Electrical and Computer Engineering, University of California, Irvine, CA 92697, USA
4Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran 1983963113, Iran

Received 30 April 2013; Accepted 29 July 2013

Academic Editors: H. J. De Los Santos, M. Hopkinson, and H. Kim

Copyright © 2013 Shima Mehrabi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dynamic/static full adder cell is presented in this paper with the aim of reaching high efficiency. The midoutputs are obtained from a Multi-output dynamic module. Then, a multiplexer generates final outputs in the static part. Several conventional and state-of-the-art dynamic adders are also surveyed and compared in the paper. All circuits are simulated by HSPICE with 32 nm CNFET technology. The proposed design is the fastest dynamic adder cell. In addition, it has approximately 5% higher efficiency in terms of PDP than the second most high-performance cell, which is DDCVS.