Research Article

DFAL: Diode-Free Adiabatic Logic Circuits

Table 2

Comparison of power, delay and PDP with frequency at 20 fF in 10 cycles of charging/discharging.

Inverters1 MHz10 MHz20 MHz33 MHz50 MHz100 MHz

Power dissipation ( W)

CMOS0.1310.7141.372.263.326.98
Proposed0.0190.2040.4260.6661.142.62

Delay (ns)

CMOS0.7020.3270.2860.2650.260.252
Proposed1.290.4310.3590.3190.2910.246

PDP (fJ)

CMOS0.0920.230.390.60.861.76
Proposed0.0260.0880.1530.210.330.64

Energy saving %

71.761.760.76561.663.6

Adiabatic gain

3.542.612.542.862.62.75