DFAL: Diode-Free Adiabatic Logic Circuits

Table 3

Comparison of power, delay and PDP with load capacitance at 𝑓_pc=80 MHz and 𝑓_in=40 MHz in 10 cycles of charging/discharging.

Inverters	10 fF	30 fF	50 fF	80 fF	100 fF	200 fF
	Power dissipation (𝜇W)
CMOS	1.44	3.93	6.42	10.1	12.7	24.8
Proposed	0.463	1.36	2.35	4	5.18	10.8
	Delay (ns)
CMOS	0.152	0.376	0.601	0.934	1.166	2.275
Proposed	0.187	0.376	0.51	0.691	0.808	1.42
	PDP (fJ)
CMOS	0.219	1.48	3.86	9.43	14.8	56.4
Proposed	0.087	0.511	1.19	2.77	4.19	15.34
	Energy saving %
	60.2	65.4	69.1	70.6	71.6	72.8
	Adiabatic gain
	2.51	2.89	3.24	3.40	3.53	3.67