Research Article
DFAL: Diode-Free Adiabatic Logic Circuits
Table 4
Comparison of proposed DFAL and CMOS circuits at
MHz,
MHz in 10 cycles of charging/discharging.
| Circuits | NOT | NAND | NOR | XOR | HA* | FA* | Dff* | Multiplier |
| | Power dissipation (W) | |
| CMOS | 0.247 | 0.563 | 0.367 | 0.885 | 2.41 | 7.97 | 5.02 | 136 | Proposed | 0.041 | 0.17 | 0.107 | 0.216 | 0.281 | 0.719 | 0.786 | 32.3 |
| | Delay (ns) | |
| CMOS | 0.003 | 0.004 | 0.005 | 0.12 | 0.12 | 0.25 | 0.23 | 0.88 | Proposed | 0.005 | 0.007 | 0.0054 | 0.11 | 0.15 | 0.45 | 0.37 | 1.71 |
| | PDP (fJ) | |
| CMOS | 0.00074 | 0.0023 | 0.002 | 0.11 | 0.29 | 1.99 | 1.15 | 119.6 | Proposed | 0.0002 | 0.0012 | 0.0006 | 0.02 | 0.04 | 0.324 | 0.29 | 55.2 |
| | Energy saving % | |
| | 72.9 | 47.8 | 70 | 81.8 | 86.2 | 83.7 | 74.7 | 53.8 |
| | Adiabatic gain | |
| | 3.7 | 1.91 | 3.33 | 5.5 | 7.25 | 6.14 | 3.96 | 2.16 |
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*Half adder, full adder, D flip-flop.
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