Research Article

DFAL: Diode-Free Adiabatic Logic Circuits

Table 4

Comparison of proposed DFAL and CMOS circuits at  MHz,  MHz in 10 cycles of charging/discharging.

CircuitsNOTNANDNORXORHA*FA*Dff*Multiplier

Power dissipation ( W)

CMOS0.2470.5630.3670.8852.417.975.02136
Proposed0.0410.170.1070.2160.2810.7190.78632.3

Delay (ns)

CMOS0.0030.0040.0050.120.120.250.230.88
Proposed0.0050.0070.00540.110.150.450.371.71

PDP (fJ)

CMOS0.000740.00230.0020.110.291.991.15119.6
Proposed0.00020.00120.00060.020.040.3240.2955.2

Energy saving %

72.947.87081.886.283.774.753.8

Adiabatic gain

3.71.913.335.57.256.143.962.16

*Half adder, full adder, D flip-flop.