Table of Contents
ISRN Machine Vision
Volume 2013, Article ID 820216, 6 pages
Research Article

Area Optimized FPGA-Based Implementation of The Sobel Compass Edge Detector

1CSIR-Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani, Rajasthan 333031, India
2Electronic Science Department, Kurukshetra University, Kurukshetra, Haryana 136119, India

Received 22 December 2012; Accepted 4 February 2013

Academic Editors: V. Alchanatis and A. Nikolaidis

Copyright © 2013 Sanjay Singh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a new FPGA resource optimized hardware architecture for real-time edge detection using the Sobel compass operator. The architecture uses a single processing element to compute the gradient for all directions. This greatly economizes on the FPGA resources' usages (more than 40% reduction) while maintaining real-time video frame rates. The measured performance of the architecture is 50 fps for standard PAL size video and 200 fps for CIF size video. The use of pipelining further improved the performance (185 fps for PAL size video and 740 fps for CIF size video) without significant increase in FPGA resources.