Area Optimized FPGA-Based Implementation of The Sobel Compass Edge Detector

Table 1

Comparison of synthesis results.

Synthesis parameters	Standard [6, 7]; Figures 3–4	Proposed Figures 4 and 5; (percentage of reduction)	Proposed pipelined; Figures 5–6 (percentage of reduction)
FPGA slices	67	40 (40.3%)	42 (37.3%)
Slice LUTs	222	109 (50.9%)	117 (47.3%)
LUT FF pairs	222	118 (46.8%)	133 (40.1%)
Slice register	2	40	95
Route-thrus	16	2 (87.5%)	2 (87.5%)