Abstract
Differential Voltage Current Controlled Current Feedback Operational Amplifier is an attractive active element for realizing resistorless filters with a minimum active component count. This is verified through a design example, where a 3rd-order leapfrog filter has been realized using the AMS 0.35 μm CMOS process design kit. The performance of the Differential Voltage Current Controlled Current Feedback Operational Amplifier filter is evaluated and compared with that obtained by the corresponding filter, where Differential Voltage Current Controlled Current Conveyors have been employed.
1. Introduction
The Current Feedback Operational Amplifier (CFOA) is a four terminal active element which offers particularly higher speed, higher slew rate, and better bandwidth than those achieved by the conventional voltage-mode op amps [1, 2]. A number of CFOA topologies with terminals of single type have been already introduced in the literature [3–6]. Enhanced CFOA topologies, including Fully Differential CFOAs (FDCFOAs) [7–10], Differential Voltage CFOAs (DVCFOAs) [11, 12], have been also published. Comparative studies of CFOAs and DVCFOAs have been performed in [4, 13], respectively.
The realization of time-constants in filters, where the aforementioned types of CFOAs are utilized, is achieved by employing passive resistors. This is a drawback with respect to the nowadays analog filter realization trend, where resistorless filter structures with electronic tuning capability are preferred. As a solution, active resistors could be employed, but the performance of the resulted filter configurations in terms of linearity is worsened in this case.
Resistorless topologies using CFOAs could be realized by employing the current controlled CFOA (CCCFOA) in [14]. The core of this active cell is constructed from translinear loops formed by a bipolar transistor. In addition, the minimum supply voltage requirement is equal to , where and are the base-emitter voltage of a bipolar transistor and saturation voltage of an MOS transistor, respectively.
In order the CFOA filters to be compatible with the nowadays trend, a novel enhanced version of CFOA, mentioned as Differential Voltage Current Controlled Current Feedback Operational Amplifier (DVCCCFOA), will be employed for the realization of active filters. This cell has also the benefit for operating in a low-voltage power supply environment. As it will be proved through comparison results, the employment of the DVCCCFOA offers a reduced number of active component counts in comparison with the corresponding realizations, where Differential Voltage Current Controlled Current Conveyors (DVCCCIIs) are utilized as active elements.
The paper is organized as follows: the DVCCCFOA configuration is presented in Section 2, while integrator blocks are given in Section 3. As a design example, a 3rd-order leapfrog filter has been realized using the AMS 0.35 μm CMOS process design kit, and the most important performance factors have been evaluated in Section 4. In addition, the same filter topology has been realized using DVCCCIIs as active elements, and its performance has been compared with that of the DVCCCFOA filter. All the above have been achieved using the Analog Design Environment tool of the Cadence software.
2. Low-Voltage DVCCCFOA
A DVCCCFOA topology is depicted in Figure 1(a), while the corresponding notation is given in Figure 1(b). Due to the used single power supply voltage, a dc voltage mentioned as is employed in order to keep all the MOS transistors in saturation. This cell is constructed from the following three stages: (a)a voltage subtraction input stage formed by transistors , and the associated dc current sources, in order to realize the following relationship: ,(b)a current controlled current conveyor [15], which is formed by transistors and the associated dc current sources. This stage realizes the following relationships between the currents that flow through terminals and , and the voltages at terminals , , and : and , where and is the value of the transconductance parameter of transistors . Owing to the small-signal nature of transconductance, the value of the realized resistor is electronically controlled through a dc current, and this makes possible the realization of resistorless filters with electronic adjustments of their frequency characteristics,(c)a voltage buffer realized by transistors , and the associated dc current sources. Obviously, this topology is a special case of the input stage where just one input is utilized. The established expression is , implying that the voltage at node is conveyed to node through the buffer.
(a)
(b)
Concluding, the operation of DVCCCFOA could be desribed in matrix form by (1) as
Another important point is that the DVCCCFOA in Figure 1(a) is capable of operating in a low-voltage power supply environment. This is originated from the fact that the minimum supply voltage requirement is , where and are the threshold and saturation voltages of an MOS transistor, respectively. Also, the minimum value of the voltage is equal to .
It should be mentioned at this point that the voltage subtraction stage has been already used for realizing the DVCCII [16, 17]. Thus, the combination of this stage with the CCCII stage described in (b) gives a low-voltage differential voltage current controlled conveyor (DVCCII). Adding a voltage buffer to that two-stage cell, a low-voltage DVCCCFOA is resulted. Therefore, a contribution of this work is that, for the first time in the literature, the DVCCCFOA is utilized for realizing low-voltage resistorless active filters.
3. Integration Blocks with the DVCCCFOA
Let us consider the input-output relationship for a differential input lossless integrator, given by (2) as where is the corresponding time-constant.
Using a DVCCCII as active element, the derived configuration is depicted in Figure 2(a), where the realized time constant is given by the formula: , where is the transconductance parameter of the corresponding MOS transistor. Taking into account that , where is the intrinsic transconductance factor of the MOS transistor, is its aspect ratio, and is a dc current, it is obvious that the realized time constant has electronic tuning capability through the dc current . A drawback of the topology in Figure 2(a) is that it is sensitive to the loading effect; in other words, a cascade connection is possible only with high-input impedance stages.
(a)
(b)
(c)
The integrated topology in Figure 2(b) does not suffer from this drawback due to the voltage buffering operation performed by the DVCFOA cell. On the other hand, the realized time-constant has now the form of , and, consequently, the benefit of resistorless realization is lost.
The lossless integrator configuration using DVCCCFOA, depicted in Figure 2(c), simultaneously offers a resistorless realization with a time-constant given by the same expression as that for the topology in Figure 2(a) and direct cascade connection capability. This has been achieved without losing the benefit of employing a grounded capacitor, which is also the case for the topologies in Figures 2(a) and 2(b).
The expression of a differential input lossy integrator is given by (3) as The corresponding realizations using DVCCCII, DVCFOA, and DVCCFOA as active elements are demonstrated in Figures 3(a)–3(c), respectively. Inspecting the resistorless realizations in Figures 3(a) and 3(c), it is evident that the employment of DVCCCFOAs as active elements offers a reduction of the active component count. Also, it should be mentioned at this point that the integrator in Figure 3(c) preserves the cascade connection capability without the requirement of extra circuitry. Comparing the topologies in Figures 3(b) and 3(c), it is obvious that the employment of the DVCCCFOA leads to an absence of resistors without increasing the active component count.
(a)
(b)
(c)
4. Simulation and Comparison Results
The performance of the DVCCCFOA in Figure 1(a) has been evaluated through simulation results by employing the Analog Design Environment tool of the Cadence software. For this purpose, the MOS transistors models provided by the AMS 0.35 μm C35B4 CMOS process design kit have been utilized in simulations. The used bias scheme was V, V, and μA. The aspect ratio of pMOS transistors was 50 μm/2 μm, and the same ratio has been used for the pMOS transistors that realize the corresponding dc currents. The nMOS transistors have an aspect ratio of 2.5 μm/0.4 μm, while for nMOS transistors used for the realization of the corresponding dc currents have 2.5 μm/1 μm.
The simulated frequency response of the current conveying between terminals and is depicted in Figure 4(a), while the corresponding plot for the voltage conveying between nodes and is given in Figure 4(b). The cutoff frequencies of these responses are 1 GHz and 66 MHz, respectively. The realized values of the intrinsic resistance , as a function of the dc bias current, are given in the plot of Figure 4(c).
(a)
(b)
(c)
As a design example, a 3rd-order lowpass filter will be realized using the leapfrog method. The corresponding Signal Flow Graph (SFG) is depicted in Figure 5, while the obtained filter topology is presented in Figure 6. The obtained value of transconductance of transistors was about 116.3 μS. In order to realize a Butterworth lowpass filter transfer function with a cutoff frequency MHz, the calculated values of capacitors were pF and pF.
The dc power dissipation of the filter was 720 μW. The simulated frequency response is given in Figure 7, where the cutoff frequency was 5.06 MHz. The linear performance of the filter has been evaluated by applying a 10 kHz input signal and variable amplitude. The Total Harmonic Distortion (THD) plot as a function of the amplitude of the input signal is given in Figure 8, where a THD equal to 1% has been measured for input signal amplitude equal to 320 mV.
Performing an integration of the noise within the passband of the filter, the obtained rms value of the input referred noise was 300 μV. Thus, the predicted value of the Dynamic Range (DR) of the filter will be 57.5 dB.
The tuning capability of the filter in Figure 6 has been demonstrated in Figure 9, where the frequency responses at μA, 12 μA, and 20 μA are simultaneously given. The obtained cutoff frequencies were 3.4 MHz, 5.06 MHz, and 6.7 MHz, respectively, and they are close to the theoretically expected values 3.6 MHz, 5 MHz, and 6.5 MHz.
The sensitivity performance of the filter in Figure 6 has been evaluated through the utilization of the Monte-Carlo analysis offered by the Analog Design Environment of the Cadence software. The derived statistical histograms about the gain and the cutoff frequency of the filter are given in Figure 10, where the values of the standard deviation of the gain and cutoff frequency were 3.2% and 210 KHz, respectively. Thus, the filter in Figure 6 has reasonable sensitivity characteristics.
(a)
(b)
The performance of the filter realized using DVCCCFOAs as active elements will be compared with that offered by the corresponding filter where DVCCCIIs are used as active elements. The derived filter topology is depicted in Figure 11, where the DVCCCIIs are realized by omitting the buffer stage at the output of the cell in Figure 1(a). In order to achieve fair comparison results, the same bias scheme as in the case of the filter in Figure 6 has been employed. The obtained performance factors of the filter in Figure 11 are given in Table 1, where the corresponding factors of the filter in Figure 6 are also summarized. According to these results, the filter realized using DVCCCFOAs offers significant improvement in terms of linearity and Dynamic Range, while the other performance parameters have been also improved.
5. Conclusions
The introduced DVCCCFOA meets the nowadays trends for designing filters suitable for low-voltage operations and electronic tuning capabilities of their frequency characteristics. The provided design example confirmed its benefits in terms of versatility and design flexibility. In addition, the comparison results confirmed the benefits of reduced active component count and improved linear performance. Thus, the DVCCCFOA could be considered as an attractive candidate for realizing high performance analog processing systems.
Conflict of Interests
The authors of the paper declare that they do not have any conflict of interests with the commercial identities mentioned in the paper.