Table of Contents
ISRN Electronics
Volume 2013, Article ID 987179, 6 pages
http://dx.doi.org/10.1155/2013/987179
Research Article

A Low Power Voltage Controlled Oscillator Design

Department of Electronics & Communication Engineering, Guru Jambheshwar University of Science & Technology, Hisar 125001, India

Received 5 April 2013; Accepted 25 April 2013

Academic Editors: S. Hall, R. Luzzi, V. McGahay, P. Wachulak, and X. Yang

Copyright © 2013 Manoj Kumar. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The performance of voltage controlled oscillator (VCO) is of great importance for any telecommunication or data transmission network. Here, voltage controlled oscillators (VCOs) using three-transistor NAND gates have been designed. New delay cell with three-transistor NAND gate has been used for designing the ring based VCO circuits. Three-, five-, and seven-stage VCOs have been proposed. Output frequency has been controlled with supply voltage variation from 1.8 V to 2.4 V. Three stage VCO shows output frequency variation in the range of 3.2909 GHz to 4.2280 GHz whereas power consumption varies in the range of 335.4071 μW to 486.1816 μW. Five-stage VCO depicts frequency in the range of 1.9406 GHz to 2.5769 GHz with power consumption variation from 559.0118 μW to 810.3027 μW. Moreover a seven-stage VCO shows frequency variation from 1.3984 GHz to 1.8077 GHz. Power consumption of seven-stage VCO varies from 782.6165 μW to 1134.400 μW. Phase noise results for these VCOs have also been obtained. Power consumption, output frequency, and phase noise results of proposed circuits have been compared with earlier reported circuits, and the proposed circuits show significant improvements.