Table of Contents
ISRN Electronics
Volume 2014, Article ID 357184, 6 pages
Research Article

Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer

Electronics and Communication Engineering Department, NSIT, New Delhi, India

Received 11 November 2013; Accepted 24 December 2013; Published 9 February 2014

Academic Editors: H.-C. Chen and S. Gift

Copyright © 2014 Maneesha Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.