Table of Contents
ISRN Electronics
Volume 2014, Article ID 357184, 6 pages
http://dx.doi.org/10.1155/2014/357184
Research Article

Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer

Electronics and Communication Engineering Department, NSIT, New Delhi, India

Received 11 November 2013; Accepted 24 December 2013; Published 9 February 2014

Academic Editors: H.-C. Chen and S. Gift

Copyright © 2014 Maneesha Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. S. S. Rajput and S. S. Jamuar, “Low voltage analog circuit design techniques,” IEEE Circuits and Systems Magazine, vol. 2, no. 1, pp. 24–42, 2002. View at Publisher · View at Google Scholar · View at Scopus
  2. Y. Haga, H. Zare-Hoseini, L. Berkovi, and I. Kale, “Design of a 0.8 volt fully differential CMOS OTA using the bulk-driven technique,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '05), vol. 1, pp. 220–223, May 2005. View at Publisher · View at Google Scholar · View at Scopus
  3. B. Aggarwal, M. Gupta, and A. K. Gupta, “Analysis of low voltage bulk-driven self-biased high swing cascode current mirror,” Microelectronics Journal, vol. 44, no. 3, pp. 225–235, 2013. View at Publisher · View at Google Scholar
  4. Y. Berg, T. S. Lande, and S. Naess, “Low-voltage floating-gate current mirrors,” in Proceedings of the 10th Annual IEEE International ASIC Conference and Exhibit, pp. 21–24, September 1997. View at Scopus
  5. T. S. Lande, D. T. Wisland, T. Saether, and Y. Berg, “FLOGIC—floating-gate logic for low-power operation,” in Proceedings of the 3rd IEEE International Conference on Electronics, Circuits, and Systems (ICECS '96), pp. 1041–1044, October 1996. View at Scopus
  6. R. Pandey and M. Gupta, “A novel voltage-controlled grounded resistor using FGMOS technique,” in Proceedings of the International Multimedia, Signal Processing and Communication Technologies, pp. 16–19, March 2009. View at Publisher · View at Google Scholar · View at Scopus
  7. M. Gupta and R. Pandey, “FGMOS based voltage-controlled resistor and its applications,” Microelectronics Journal, vol. 41, no. 1, pp. 25–32, 2010. View at Publisher · View at Google Scholar · View at Scopus
  8. M. Gupta and R. Pandey, “Low-voltage FGMOS based analog building blocks,” Microelectronics Journal, vol. 42, no. 6, pp. 903–912, 2011. View at Publisher · View at Google Scholar · View at Scopus
  9. R. Pandey and M. Gupta, “FGMOS based tunable grounded resistor,” Analog Integrated Circuits and Signal Processing, vol. 65, no. 3, pp. 437–443, 2010. View at Publisher · View at Google Scholar · View at Scopus
  10. E. Rodriguez-Villegas, Low Power and Low Voltage Circuit Design with the FGMOS Transistor, vol. 20 of IET Circuits, Devices & Systems Series, The Institution of Engineering and Technology, London, UK, 2006.
  11. E. Seevinck and R. F. Wassenaar, “A versatile CMOS linear transconductor /square-law function,” IEEE Journal of Solid-State Circuits, vol. 22, no. 3, pp. 366–377, 1986. View at Google Scholar · View at Scopus
  12. G. Giustolisi, G. Palmisano, and G. Palumbo, “1.5 V power supply CMOS voltage squarer,” Electronics Letters, vol. 33, no. 13, pp. 1134–1136, 1997. View at Google Scholar · View at Scopus
  13. A. J. Lopez-Martin, J. Ramirez-Angulo, R. Chintham, and R. G. Carvajal, “Class AB CMOS analogue squarer circuit,” Electronics Letters, vol. 43, no. 20, pp. 1059–1060, 2007. View at Publisher · View at Google Scholar · View at Scopus
  14. S. Vlassis and S. Siskos, “Analogue squarer and multiplier based on floating-gate MOS transistors,” Electronics Letters, vol. 34, no. 9, pp. 825–826, 1998. View at Publisher · View at Google Scholar · View at Scopus
  15. S.-I. Liu and Y.-S. Hwang, “CMOS squarer and four-quadrant multiplier,” IEEE Transactions on Circuits and Systems-I, vol. 42, no. 2, pp. 119–122, 1995. View at Publisher · View at Google Scholar
  16. S. Minaei and E. Yuce, “New squarer circuits and a current-mode full-wave rectifier topology suitable for integration,” Radioengineering, vol. 19, no. 4, pp. 657–661, 2010. View at Google Scholar · View at Scopus
  17. R. Srivastava, M. Gupta, and U. Singh, “FGMOS transistor based low voltage and low power fully programmable gaussian function generator,” Analog Integrated Circuits & Signal Processing, vol. 78, no. 1, pp. 245–252, 2014. View at Publisher · View at Google Scholar
  18. S. Vlassis and S. Siskos, “Differential-voltage attenuator based on floating-gate MOS transistors and its applications,” IEEE Transactions on Circuits and Systems I, vol. 48, no. 11, pp. 1372–1378, 2001. View at Publisher · View at Google Scholar · View at Scopus
  19. E. Rodriguez-Villegas and H. Barnes, “Solution to trapped charge in FGMOS transistors,” Electronics Letters, vol. 39, no. 19, pp. 1416–1417, 2003. View at Publisher · View at Google Scholar · View at Scopus
  20. E. Rodriguez-Villegas, M. Jimenez, and R. G. Carvajal, “On dealing with the charge trapped in Floating-Gate MOS (FGMOS) transistors,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 2, pp. 156–160, 2007. View at Publisher · View at Google Scholar · View at Scopus
  21. I. Navarro, A. J. López-Martín, C. A. De La Cruz, and A. Carlosena, “A compact four-quadrant Floating-Gate MOS multiplier,” Analog Integrated Circuits and Signal Processing, vol. 41, no. 2-3, pp. 159–166, 2004. View at Publisher · View at Google Scholar · View at Scopus