Table of Contents
ISRN Electronics
Volume 2014, Article ID 857912, 9 pages
Research Article

Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector

1IC Design Group, CSIR-Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani, Rajasthan 333031, India
2CSIR-CEERI, Academy of Scientific & Innovative Research (AcSIR), Pilani, Rajasthan 333031, India
3Electronic Science Department, Kurukshetra University, Kurukshetra, Haryana 136119, India

Received 30 January 2014; Accepted 20 February 2014; Published 6 April 2014

Academic Editors: T. Laopoulos and X. Yang

Copyright © 2014 Sanjay Singh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a comprehensive review and a comparative study of various hardware/FPGA implementations of Sobel edge detector and explored different architectures for Sobel gradient computation unit in order to show the various trade-offs involved in choosing one over another. The different architectures using pipelining and/or parallelism (key methodologies for improving the performance/frame rates) are explored for gradient computation unit in Sobel edge detector. How the different architectures affected performance (in terms of video frame rate and image size) and area (in terms of FPGA resources usages) has been demonstrated. By exploiting the trade-offs between video frame rate, image size, and FPGA resources a designer should be able to find an optimal architecture for a given application.