Formal Modeling and Verification for MVB

Listing 2

PROMELA codes of the synchronous bus.

active proctype Synchronous_Bus ( ) {

atomic  {

  if

  /*BA_0 as the Regular Master*/

  ::     (BA_0. cur == REGULAR_MASTER && BA_1. cur != REGULAR_MASTER) ->

      BA_0. output ? frame; BA_0. input ! frame;

      master_type = frame. type;

       /*Master Frame from BA_0 to BA_1*/

       if

       ::  true -> frame. type = LOST;

       ::  true -> frame. type = master_type;

       fi;

      BA_1. input ! frame;

       /*Slave Frame from BA_1 to BA_0*/

       if

       :: frame. recv == 1 -> …  /*Answer the Master Frame*/

       ::  else -> skip;

       fi;

    …  /* BA_1 as the Regular Master */

    :: (BA_0. cur!=REGULAR_MASTER && BA_1. cur!=REGULAR_MASTER) ->

       frame. type = LOST;  /*No Regular Master*/

       BA_0. input ! frame; BA_1. input ! frame;

    ::  else -> …  /*Receive data from output channel of BAs in Regular Mastership*/

    fi;

    …

}