Table of Contents Author Guidelines Submit a Manuscript
Journal of Applied Mathematics
Volume 2014, Article ID 194574, 15 pages
http://dx.doi.org/10.1155/2014/194574
Research Article

Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions

1School of Computer and Information Technology, Beijing Jiaotong University, Beijing 10044, China
2School of Electronic and Information Engineering, Lanzhou Jiaotong University, Lanzhou 730070, China
3G & S Labs, School of Software of Dalian University of Technology, Dalian 116620, China
4Guangxi Key Laboratory of Hybrid Computation and IC Design Analysis, Guangxi University for Nationalities, Nanning 530006, China

Received 13 February 2014; Accepted 7 April 2014; Published 11 June 2014

Academic Editor: Xiaoyu Song

Copyright © 2014 Ning Zhou et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. IEEE System Verilog Working Group, IEEE Standard for SystemVerilog C Unified Hardware Design, Specification, and Verification (IEEE Std 1800-2005). IEEE, 2005.
  2. “IEEE draft standard for system verilog—unified hardware design, specification, and verification language,” IEEE P1800/D3, 2011.
  3. R. Wille, G. Fey, M. Messing, G. Angst, L. Linhard, and R. Drechsler, “Identifying a subset of SystemVerilog assertions for efficient bounded model checking,” in Proceedings of the 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD '08), pp. 542–549, September 2008. View at Publisher · View at Google Scholar · View at Scopus
  4. L. Darringer, “Application of program verification techniques to hardware verification,” in Proceedings of the IEEE-ACM Design Automation Conference, pp. 375–381, 1979.
  5. G. S. Avrunin, “Symbolic model checking using algebraic geometry,” in Proceedings of the 8th International Conference on Computer Aided Verification, vol. CAV96, pp. 26–37, Springer, London, UK, 1996.
  6. W. B. Mao and J. Z. Wu, “Application of Wus method to symbolic model checking,” in Proceedings of the 2005 international Symposium on Symbolic and Algebraic Computation (ISSAC '05), pp. 237–244, ACM Press, Beijing, China, 2005. View at Publisher · View at Google Scholar · View at MathSciNet
  7. J. Wu and L. Zhao, “Multi-valued model checking via groebner basis approach,” in Proceedings of the 1st Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering (TASE '07), pp. 35–44, IEEE Computer Society Press, June 2007. View at Publisher · View at Google Scholar · View at Scopus
  8. N. Zhou, J. Wu, and X. Gao, “Algebraic verification method for SEREs properties via Groebner bases approaches,” Journal of Applied Mathematics, vol. 2013, Article ID 272781, 10 pages, 2013. View at Publisher · View at Google Scholar · View at Zentralblatt MATH · View at MathSciNet
  9. X. Gao, N. Zhou, J. Wu, and D. Li, “Wu’s characteristic set method for SystemVerilog assertions verification,” Journal of Applied Mathematics, vol. 2013, Article ID 740194, 14 pages, 2013. View at Publisher · View at Google Scholar
  10. J. Little, D. Cox, and D. O'Shea, Ideals, Varieties, and Algorithms, Springer, New York, NY, USA, 1992. View at MathSciNet
  11. T. Becker and V. Weispfenning, Gröbner Bases: A Computational Approach to Commutative Algebra, Springer, New York, NY, USA, 1993. View at Publisher · View at Google Scholar · View at MathSciNet
  12. B. Buchberger, “Groebner bases: an algorithmic method in polynomial ideal theory,” in Multidimensional Systems Theory, pp. 184–232, 1985. View at Google Scholar
  13. S. B. Akers, “Binary decision diagrams,” IEEE Transactions on Computers C, vol. 27, no. 6, pp. 509–516, 1978. View at Google Scholar · View at Scopus
  14. S. Hoereth and R. Drechsler, “Formal verification of word-level specifications,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 52–58, Munich, Germany, 1999.
  15. Y. M. Ryabukhin, “Boolean ring,” in Encyclopaedia of Mathematics, Springer, Michiel, Germany, 2001. View at Google Scholar
  16. S. Das, R. Mohanty, P. Dasgupta, and P. P. Chakrabarti, “Synthesis of system verilog assertions,” in Proceedings of the Conference on Design, Automation and Test in Europe: Designers’ Forum (DATE ’06), pp. 70–75, European Design and Automation Association, Leuven, Belgium, March 2006. View at Publisher · View at Google Scholar · View at Scopus
  17. C.-J. Seger and R. E. Bryant, “Formal verification by symbolic evaluation of partially-ordered trajectories,” Formal Methods in System Design, vol. 6, no. 2, pp. 147–190, 1995. View at Publisher · View at Google Scholar · View at Scopus
  18. D. Cox, J. Little, and D. O'Shea, Ideals, Varieties, and Algorithms An Introduction to Computational Algebraic Geometry and Commutative Algebra, Undergraduate Texts in Mathematics, Springer, New York, 3rd edition, 2007. View at Publisher · View at Google Scholar · View at MathSciNet