Research Article
Analysis of Parallel Multidimensional Wave Digital Filtering Network on IBM Cell Broadband Engine
Table 1
Schedule tables: (a) MDFG. (b) The retimed MDFG.
(a) |
| Clock cycle (level number) | Operations |
| 0 | D1 | D2 | D3 | D4 | 1 | E1 | E2 | E3 | E4 | 2 | EF1 | F23 | EF4 | 3 | Gc1 | G23 | Gc2 | 4 | F1 | H2 | H3 | F4 | 5 | G1 | | | G4 | 6 | H1 | | | H4 | 7 | C1 C2 | C3 C4 | Processor | P0 |
|
|
(b) |
| Clock cycle (level number) | Operations |
| 0 | D1 | E1 | EF1 | Gc1 | F1 | G1 | H1 | C1 | 0 | D2 | E2 | F23 | G23 | H2 | | | C2 | 0 | D3 | E3 | H3 | | | C3 | 0 | D4 | E4 | EF4 | Gc2 | F4 | G4 | H4 | C4 | Processor | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P0 |
|
|