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Journal of Computer Networks and Communications
Volume 2011, Article ID 405697, 6 pages
Research Article

Novel NoC Topology Construction for High-Performance Communications

1Department of Computer Science and Engineering, Rajalakshmi Engineering College, Thandalam Chennai 602 105, India
2Department of Computer Science and Engineering, R.M.K Engineering College, Chennai 600 040, India

Received 12 November 2010; Accepted 7 March 2011

Academic Editor: Youyun Xu

Copyright © 2011 P. Ezhumalai et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation.